[llvm] [VPlan] Handle VPWidenCastRecipe without underlying value in EVL transform (PR #120194)

[Luke Lau via llvm-commits]

lukel97 wrote:

> Could you share the IR causing the problem?

```llvm
define void @hpel_filter(ptr %dstv, ptr %src, i64 %wide.trip.count) {
entry:
  br label %for.body4

for.cond.cleanup3.loopexit:                       ; preds = %for.body4
  ret void

for.body4:                                        ; preds = %for.body4, %entry
  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body4 ]
  %arrayidx13 = getelementptr i8, ptr %src, i64 %indvars.iv
  %0 = load i8, ptr %arrayidx13, align 1
  %conv14 = zext i8 %0 to i32
  %mul21.neg = mul i32 %conv14, 0
  %add33 = ashr i32 %conv14, 0
  %shr = or i32 %add33, 0
  %tobool.not.i = icmp ult i32 %conv14, 0
  %cond.i = select i1 %tobool.not.i, i32 %shr, i32 0
  %conv.i = trunc i32 %cond.i to i8
  store i8 %conv.i, ptr %dstv, align 1
  %conv36 = trunc i32 %mul21.neg to i16
  store i16 %conv36, ptr null, align 2
  %indvars.iv.next = add i64 %indvars.iv, 1
  %exitcond.not = icmp eq i64 %indvars.iv, %wide.trip.count
  br i1 %exitcond.not, label %for.cond.cleanup3.loopexit, label %for.body4
}
```

I'm able to reproduce the assertion with `opt -disable-output -passes=loop-vectorize -mtriple riscv64 -mattr=+v -disable-output -force-tail-folding-style=data-with-evl  -prefer-predicate-over-epilogue=predicate-dont-vectorize`

FWIW I think this might be non-deterministic. Building opt with asan+ubsan seems to cause the assertion to go away, but nothing gets reported

https://github.com/llvm/llvm-project/pull/120194