[llvm] a56ca3a - [test] Don't test initial ".text" in llvm-mc --disassemble output
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 16 23:25:09 PST 2024
Author: Fangrui Song
Date: 2024-12-16T23:24:34-08:00
New Revision: a56ca3a4e4f9ee8a7ce231cf7b162c4688524fdf
URL: https://github.com/llvm/llvm-project/commit/a56ca3a4e4f9ee8a7ce231cf7b162c4688524fdf
DIFF: https://github.com/llvm/llvm-project/commit/a56ca3a4e4f9ee8a7ce231cf7b162c4688524fdf.diff
LOG: [test] Don't test initial ".text" in llvm-mc --disassemble output
This kludge will go away after #120185.
Added:
Modified:
llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s
llvm/test/MC/Disassembler/AArch64/armv8r-sysreg.txt
llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt
llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt
llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt
llvm/test/MC/Disassembler/Mips/eva/valid_R6-eva.txt
llvm/test/MC/Disassembler/Mips/eva/valid_preR6-eva.txt
llvm/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
llvm/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
llvm/test/MC/Disassembler/RISCV/colored.txt
llvm/test/MC/Disassembler/WebAssembly/wasm-error.txt
llvm/test/MC/Disassembler/WebAssembly/wasm.txt
Removed:
################################################################################
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s b/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s
index b06b7e1a993809..a42f10986b681f 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s
@@ -67,8 +67,7 @@
[0xa0,0xdb,0x3c,0xd5]
[0xc0,0xdb,0x3c,0xd5]
[0xe0,0xdb,0x3c,0xd5]
-// CHECK: .text
-// CHECK-NEXT: msr S3_3_C13_C2_6, x0 // encoding: [0xc0,0xd2,0x1b,0xd5]
+// CHECK: msr S3_3_C13_C2_6, x0 // encoding: [0xc0,0xd2,0x1b,0xd5]
// CHECK-NEXT: mrs x0, AMCG1IDR_EL0 // encoding: [0xc0,0xd2,0x3b,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF00_EL2, x0 // encoding: [0x00,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF01_EL2, x0 // encoding: [0x20,0xd8,0x1c,0xd5]
@@ -134,8 +133,7 @@
// CHECK-NEXT: mrs x0, AMEVCNTVOFF113_EL2 // encoding: [0xa0,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF114_EL2 // encoding: [0xc0,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF115_EL2 // encoding: [0xe0,0xdb,0x3c,0xd5]
-// NOAMVS: .text
-// NOAMVS-NEXT: msr S3_3_C13_C2_6, x0 // encoding: [0xc0,0xd2,0x1b,0xd5]
+// NOAMVS: msr S3_3_C13_C2_6, x0 // encoding: [0xc0,0xd2,0x1b,0xd5]
// NOAMVS-NEXT: mrs x0, S3_3_C13_C2_6 // encoding: [0xc0,0xd2,0x3b,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C8_0, x0 // encoding: [0x00,0xd8,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C8_1, x0 // encoding: [0x20,0xd8,0x1c,0xd5]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8r-sysreg.txt b/llvm/test/MC/Disassembler/AArch64/armv8r-sysreg.txt
index ba675c6de532b7..262185759700d6 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8r-sysreg.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8r-sysreg.txt
@@ -286,8 +286,7 @@
[0xbe,0x6f,0x1c,0xd5]
[0x20,0xd0,0x1c,0xd5]
-// CHECK: .text
-// CHECK-NEXT: mrs x0, VSCTLR_EL2
+// CHECK: mrs x0, VSCTLR_EL2
// CHECK-NEXT: mrs x0, MPUIR_EL1
// CHECK-NEXT: mrs x0, MPUIR_EL2
// CHECK-NEXT: mrs x0, PRENR_EL1
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
index 7073ade6a309b6..4cde11f38dde15 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-lsui.txt
@@ -186,8 +186,7 @@
[0x5f,0x34,0x20,0x59]
[0xff,0x37,0x22,0x59]
-# CHECK: .text
-# CHECK-NEXT: ldtxr x9, [sp]
+# CHECK: ldtxr x9, [sp]
# CHECK-NEXT: ldtxr x9, [sp]
# CHECK-NEXT: ldtxr x10, [x11]
# CHECK-NEXT: ldtxr x10, [x11]
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt
index ccc65e747bc0b4..5c3b57a871b9e5 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-occmo.txt
@@ -5,8 +5,7 @@
[0x0d,0x7b,0x0b,0xd5]
[0xe1,0x7b,0x0b,0xd5]
-# CHECK: .text
-# CHECK-NEXT: dc civaoc, x12
+# CHECK: dc civaoc, x12
# CHECK-NEXT: dc cigdvaoc, x0
# CHECK-NEXT: dc cvaoc, x13
# CHECK-NEXT: dc cgdvaoc, x1
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt
index 0c73b2248849d5..3855ce035a4c1c 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-pcdphint.txt
@@ -4,6 +4,5 @@
[0x1f,0x96,0x01,0xd5]
[0x3f,0x96,0x01,0xd5]
-# CHECK: .text
-# CHECK-NEXT: stshh keep
+# CHECK: stshh keep
# CHECK-NEXT: stshh strm
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
index a641731b2f1b2a..c5d074bf0394f1 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-rme-gpc3.txt
@@ -5,7 +5,6 @@
[0xa3,0x21,0x3e,0xd5]
[0xa4,0x21,0x1e,0xd5]
-# CHECK: .text
-# CHECK-NEXT: sys #6, c7, c0, #0
+# CHECK: sys #6, c7, c0, #0
# CHECK-NEXT: mrs x3, GPCBW_EL3
# CHECK-NEXT: msr GPCBW_EL3, x4
diff --git a/llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt b/llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt
index 1401af18aad5d3..30d0a603218814 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt
@@ -51,8 +51,7 @@
[0x23,0x14,0x1d,0xd5]
[0xa3,0x14,0x18,0xd5]
-# CHECK: .text
-# CHECK-NEXT: mrs x3, SCTLRMASK_EL1
+# CHECK: mrs x3, SCTLRMASK_EL1
# CHECK-NEXT: mrs x3, SCTLRMASK_EL2
# CHECK-NEXT: mrs x3, SCTLRMASK_EL12
# CHECK-NEXT: mrs x3, CPACRMASK_EL1
diff --git a/llvm/test/MC/Disassembler/Mips/eva/valid_R6-eva.txt b/llvm/test/MC/Disassembler/Mips/eva/valid_R6-eva.txt
index b9525ba1206f19..e81e4009f9313b 100644
--- a/llvm/test/MC/Disassembler/Mips/eva/valid_R6-eva.txt
+++ b/llvm/test/MC/Disassembler/Mips/eva/valid_R6-eva.txt
@@ -1,6 +1,5 @@
# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips32r6 -mattr=eva | FileCheck %s
# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r6 -mattr=eva | FileCheck %s
-# CHECK: .text
0x7c 0xff 0x7f 0x9b # CHECK: cachee 31, 255($7)
0x7c 0x80 0x80 0x1b # CHECK: cachee 0, -256($4)
0x7c 0x85 0xba 0x1b # CHECK: cachee 5, -140($4)
diff --git a/llvm/test/MC/Disassembler/Mips/eva/valid_preR6-eva.txt b/llvm/test/MC/Disassembler/Mips/eva/valid_preR6-eva.txt
index f364433c1c4e06..f08e835c9fe50a 100644
--- a/llvm/test/MC/Disassembler/Mips/eva/valid_preR6-eva.txt
+++ b/llvm/test/MC/Disassembler/Mips/eva/valid_preR6-eva.txt
@@ -4,7 +4,6 @@
# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r2 -mattr=eva | FileCheck %s
# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r3 -mattr=eva | FileCheck %s
# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r5 -mattr=eva | FileCheck %s
-# CHECK: .text
0x7c 0xff 0x7f 0x9b # CHECK: cachee 31, 255($7)
0x7c 0x80 0x80 0x1b # CHECK: cachee 0, -256($4)
0x7c 0x85 0xba 0x1b # CHECK: cachee 5, -140($4)
diff --git a/llvm/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt b/llvm/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
index 869d909621a194..f67d40ad8a5354 100644
--- a/llvm/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -disassemble -mcpu=mips1 | FileCheck %s
-# CHECK: .text
0x85 0xc1 0x20 0x46 # CHECK: abs.d $f6, $f24
0x45 0x82 0x00 0x46 # CHECK: abs.s $f9, $f16
0x20 0xb8 0x45 0x02 # CHECK: add $23, $18, $5
diff --git a/llvm/test/MC/Disassembler/Mips/mips1/valid-mips1.txt b/llvm/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
index a34327aaa76622..8ee467dc5f88c4 100644
--- a/llvm/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips1 | FileCheck %s
-# CHECK: .text
0x00 0x00 0x00 0x00 # CHECK: nop
0x00 0x00 0x00 0x40 # CHECK: ssnop
0x00 0x00 0x3c 0x80 # CHECK: sll $7, $zero, 18
diff --git a/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt b/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
index 77c85a2627d2b5..fcb4a43c6e6d1f 100644
--- a/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -disassemble -mcpu=mips2 | FileCheck %s
-# CHECK: .text
0x85 0xc1 0x20 0x46 # CHECK: abs.d $f6, $f24
0x45 0x82 0x00 0x46 # CHECK: abs.s $f9, $f16
0x20 0xb8 0x45 0x02 # CHECK: add $23, $18, $5
diff --git a/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt b/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
index 78d6568b2f5a4a..1427be5b2c56fd 100644
--- a/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc %s -triple=mips-unknown-linux -disassemble -mcpu=mips2 | FileCheck %s
-# CHECK: .text
0x00 0x00 0x00 0x00 # CHECK: nop
0x00 0x00 0x00 0x09 # CHECK: jr $zero
0x00 0x00 0x00 0x0d # CHECK: break
diff --git a/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt b/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
index 939b7966859932..3e577b4dfdee74 100644
--- a/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc %s -triple=mips64el-unknown-linux -disassemble -mcpu=mips3 | FileCheck %s
-# CHECK: .text
0x85 0xc1 0x20 0x46 # CHECK: abs.d $f6, $f24
0x45 0x82 0x00 0x46 # CHECK: abs.s $f9, $f16
0x20 0xb8 0x45 0x02 # CHECK: add $23, $18, $5
diff --git a/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt b/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
index 4877280000f1e5..92a1d3f48dabf2 100644
--- a/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc %s -triple=mips64-unknown-linux -disassemble -mcpu=mips3 | FileCheck %s
-# CHECK: .text
0x00 0x00 0x00 0x00 # CHECK: nop
0x00 0x00 0x00 0x09 # CHECK: jr $zero
0x00 0x00 0x00 0x0c # CHECK: syscall
diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
index 64c350e45a8773..46c488131659e0 100644
--- a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc %s -triple=mips64el-unknown-linux -disassemble -mcpu=mips4 | FileCheck %s
-# CHECK: .text
0x85 0xc1 0x20 0x46 # CHECK: abs.d $f6, $f24
0x45 0x82 0x00 0x46 # CHECK: abs.s $f9, $f16
0x20 0xb8 0x45 0x02 # CHECK: add $23, $18, $5
diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
index 2635b6bca7db91..cc16955ad428fa 100644
--- a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc %s -triple=mips64-unknown-linux -disassemble -mcpu=mips4 | FileCheck %s
-# CHECK: .text
0x00 0x00 0x00 0x00 # CHECK: nop
0x00 0x00 0x00 0x09 # CHECK: jr $zero
0x00 0x00 0x00 0x0c # CHECK: syscall
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
index 6a6f5a6ab30826..de4d68aeb7fc91 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
@@ -2,7 +2,6 @@
# Try a mips* triple to confirm that mips* vs mips64* triples no longer have
# an effect on the disassembler behaviour.
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips64r2 | FileCheck %s
-# CHECK: .text
0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
index 732b3521124543..2b2fda94a512a6 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
@@ -2,7 +2,6 @@
# Try a mips* triple to confirm that mips* vs mips64* triples no longer have
# an effect on the disassembler behaviour.
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r2 | FileCheck %s
-# CHECK: .text
0x00 0x00 0x00 0x00 # CHECK: nop
0x00 0x00 0x00 0x09 # CHECK: jr $zero
0x00 0x00 0x00 0x0c # CHECK: syscall
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
index 58ec7d52ef50e1..1e0bee1a750c1e 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips64r3 | FileCheck %s
-# CHECK: .text
0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
index 77b1ff2b74832d..90184c256f72f9 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r3 | FileCheck %s
-# CHECK: .text
0x00 0x00 0x00 0x00 # CHECK: nop
0x00 0x00 0x00 0x09 # CHECK: jr $zero
0x00 0x00 0x00 0x0c # CHECK: syscall
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
index b009d2a536d334..cd1cb67f7a797f 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mcpu=mips64r5 | FileCheck %s
-# CHECK: .text
0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
0x20 0x48 0xc7 0x00 # CHECK: add $9, $6, $7
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
index 134f338ed08434..4b5d6890268cb0 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
@@ -1,5 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mcpu=mips64r5 | FileCheck %s
-# CHECK: .text
0x00 0x00 0x00 0x00 # CHECK: nop
0x00 0x00 0x00 0x09 # CHECK: jr $zero
0x00 0x00 0x00 0x0c # CHECK: syscall
diff --git a/llvm/test/MC/Disassembler/RISCV/colored.txt b/llvm/test/MC/Disassembler/RISCV/colored.txt
index e79ae73955893a..46d7e7b4652221 100644
--- a/llvm/test/MC/Disassembler/RISCV/colored.txt
+++ b/llvm/test/MC/Disassembler/RISCV/colored.txt
@@ -1,12 +1,11 @@
# UNSUPPORTED: system-windows
-# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+zfa,+v --cdis %s | FileCheck %s --strict-whitespace --match-full-lines -check-prefixes=CHECK,ASM,ABINAME
-# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+zfa,+v -M numeric --cdis %s | FileCheck %s --strict-whitespace --match-full-lines -check-prefixes=CHECK,ASM,ARCHNAME
+# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+zfa,+v --cdis %s | FileCheck %s --strict-whitespace --match-full-lines -check-prefixes=ASM,ABINAME
+# RUN: llvm-mc -triple=riscv64 -mattr=+zcmp,+zfa,+v -M numeric --cdis %s | FileCheck %s --strict-whitespace --match-full-lines -check-prefixes=ASM,ARCHNAME
-# CHECK: .text
# Registers and immediates
0x03 0xe0 0x40 0x00
-# ABINAME-NEXT: lwu [0;36mzero[0m, [0;31m4[0m([0;36mra[0m)
-# ARCHNAME-NEXT: lwu [0;36mx0[0m, [0;31m4[0m([0;36mx1[0m)
+# ABINAME: lwu [0;36mzero[0m, [0;31m4[0m([0;36mra[0m)
+# ARCHNAME: lwu [0;36mx0[0m, [0;31m4[0m([0;36mx1[0m)
# Branch targets
0x63 0x00 0xb5 0x04
diff --git a/llvm/test/MC/Disassembler/WebAssembly/wasm-error.txt b/llvm/test/MC/Disassembler/WebAssembly/wasm-error.txt
index 200ae0db56ada3..73f12684f405d6 100644
--- a/llvm/test/MC/Disassembler/WebAssembly/wasm-error.txt
+++ b/llvm/test/MC/Disassembler/WebAssembly/wasm-error.txt
@@ -1,7 +1,5 @@
# RUN: llvm-mc --disassemble %s -triple=wasm32-unknown-unknown | FileCheck %s
-# CHECK: .text
-
# CHECK: block unknown_type
0x02 0x00
diff --git a/llvm/test/MC/Disassembler/WebAssembly/wasm.txt b/llvm/test/MC/Disassembler/WebAssembly/wasm.txt
index f6a3527fc5ed12..3a418ea32c12a9 100644
--- a/llvm/test/MC/Disassembler/WebAssembly/wasm.txt
+++ b/llvm/test/MC/Disassembler/WebAssembly/wasm.txt
@@ -1,7 +1,5 @@
# RUN: llvm-mc --disassemble %s -triple=wasm32-unknown-unknown | FileCheck %s
-# CHECK: .text
-
# CHECK: nop
0x01
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