[llvm] [RISCV] Add software pipeliner support (PR #117546)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

Thanks! @kasuga-fj 

> Hi. I am working on `MachinePipeliner` for AArch64 with the author of #79598. I would like to comment on our thoughts regarding MachinePipeliner.

Is this PR right? It refers to a PR of AMDGPU target. :-)

> 
> First, we don't think it's worthwhile for all loops. As @mshockwave mentioned, OoO is sufficient in many cases. However, there are cases where it is not enough due to HW resource limitations, for example, a loop with long a dependence chain. Our ultimate goal is to apply software pipelining only to such loops and we are now considering introducing a pragma directive to enable software pipelining to specific loops. Therefore, I don't know much about RISCV, but I agree that it should be disabled by default.

That's also my plan to make it disabled by default. :-)
And, for RISC-V, the CPUs vary from embedded 32 bits MCUs to high-performance 64 bits CPUs. These in-order cores may benefit from software pipelining. That's also my intention of this PR.

> 
> Also, there are some correctness issues in `MachinePipeliner`. The dependence analysis inside the pass is one of them, and we are now working on fixing it now (ref: #109918). Any comments or suggestions would be appreciated!

Well done! I will have a look later!
Currently, we don't have much experiences on pipeliner, so thanks for leading me to your fantastic works, I will follow that!

> 
> Finally, in our experience, Modulo Variable Expansion (#65609) tends to generate efficient code, especially when we cannot ignore the cost of register-to-register instructions, which are generated by default module scheduler. We have to implement some virtual functions for `RISCVPipelinerLoopInfo`, but I think it's worth a try.

Yeah, I noticed that before when I read the implementation of AArch64. I had a local branch for that and may post it when it is good enough. Thanks again!

https://github.com/llvm/llvm-project/pull/117546