[llvm] [AMDGPU] Pre-commit tests for "lshr + mad" fold (PR #119509)

[Vikram Hegde via llvm-commits]

================
@@ -1333,5 +1333,403 @@ define i48 @mad_i48_i48(i48 %arg0, i48 %arg1, i48 %arg2) #0 {
   ret i48 %a
 }
 
+define i64 @lshr_mad_i64_1(ptr addrspace(1) %1, ptr addrspace(1) %2) local_unnamed_addr #0 {
+; CI-LABEL: lshr_mad_i64_1:
+; CI:       ; %bb.0:
+; CI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT:    s_mov_b32 s6, 0
+; CI-NEXT:    s_mov_b32 s7, 0xf000
+; CI-NEXT:    s_mov_b32 s4, s6
+; CI-NEXT:    s_mov_b32 s5, s6
+; CI-NEXT:    buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
+; CI-NEXT:    buffer_load_dwordx2 v[2:3], v[2:3], s[4:7], 0 addr64
+; CI-NEXT:    s_movk_i32 s4, 0xfc19
+; CI-NEXT:    s_movk_i32 s6, 0xfc88
+; CI-NEXT:    s_waitcnt vmcnt(1)
+; CI-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v1, s4, v[0:1]
+; CI-NEXT:    s_waitcnt vmcnt(0)
+; CI-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], v3, s6, v[2:3]
+; CI-NEXT:    v_sub_i32_e32 v1, vcc, v5, v1
+; CI-NEXT:    v_sub_i32_e32 v2, vcc, v7, v3
+; CI-NEXT:    v_xor_b32_e32 v0, v4, v6
+; CI-NEXT:    v_xor_b32_e32 v1, v1, v2
+; CI-NEXT:    s_setpc_b64 s[30:31]
+;
+; SI-LABEL: lshr_mad_i64_1:
+; SI:       ; %bb.0:
+; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT:    s_mov_b32 s6, 0
+; SI-NEXT:    s_mov_b32 s7, 0xf000
+; SI-NEXT:    s_mov_b32 s4, s6
+; SI-NEXT:    s_mov_b32 s5, s6
+; SI-NEXT:    buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64
+; SI-NEXT:    buffer_load_dwordx2 v[2:3], v[2:3], s[4:7], 0 addr64
+; SI-NEXT:    s_movk_i32 s4, 0xfc19
+; SI-NEXT:    s_movk_i32 s5, 0xfc88
+; SI-NEXT:    s_waitcnt vmcnt(1)
+; SI-NEXT:    v_mul_hi_u32 v4, v1, s4
+; SI-NEXT:    s_waitcnt vmcnt(0)
+; SI-NEXT:    v_mul_hi_u32 v6, v3, s5
+; SI-NEXT:    v_mul_lo_u32 v5, v1, s4
+; SI-NEXT:    v_mul_lo_u32 v7, v3, s5
+; SI-NEXT:    v_sub_i32_e32 v4, vcc, v4, v1
+; SI-NEXT:    v_sub_i32_e32 v6, vcc, v6, v3
+; SI-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
+; SI-NEXT:    v_addc_u32_e32 v1, vcc, v4, v1, vcc
+; SI-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
+; SI-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; SI-NEXT:    v_xor_b32_e32 v0, v0, v2
+; SI-NEXT:    v_xor_b32_e32 v1, v1, v3
+; SI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: lshr_mad_i64_1:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    global_load_dwordx2 v[4:5], v[0:1], off
+; GFX9-NEXT:    global_load_dwordx2 v[6:7], v[2:3], off
+; GFX9-NEXT:    s_movk_i32 s4, 0xfc19
+; GFX9-NEXT:    s_movk_i32 s6, 0xfc88
+; GFX9-NEXT:    s_waitcnt vmcnt(1)
+; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v5, s4, v[4:5]
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v7, s6, v[6:7]
+; GFX9-NEXT:    v_sub_u32_e32 v1, v1, v5
+; GFX9-NEXT:    v_sub_u32_e32 v3, v3, v7
+; GFX9-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v3
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: lshr_mad_i64_1:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX11-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX11-NEXT:    s_waitcnt vmcnt(1)
+; GFX11-NEXT:    v_mad_u64_u32 v[4:5], null, 0xfffffc19, v1, v[0:1]
+; GFX11-NEXT:    s_waitcnt vmcnt(0)
+; GFX11-NEXT:    v_mad_u64_u32 v[6:7], null, 0xfffffc88, v3, v[2:3]
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_sub_nc_u32_e32 v1, v5, v1
+; GFX11-NEXT:    v_sub_nc_u32_e32 v2, v7, v3
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_xor_b32_e32 v0, v4, v6
+; GFX11-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: lshr_mad_i64_1:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT:    s_wait_expcnt 0x0
+; GFX12-NEXT:    s_wait_samplecnt 0x0
+; GFX12-NEXT:    s_wait_bvhcnt 0x0
+; GFX12-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NEXT:    global_load_b64 v[0:1], v[0:1], off
+; GFX12-NEXT:    global_load_b64 v[2:3], v[2:3], off
+; GFX12-NEXT:    s_wait_loadcnt 0x1
+; GFX12-NEXT:    v_mad_co_u64_u32 v[4:5], null, 0xfffffc19, v1, v[0:1]
+; GFX12-NEXT:    s_wait_loadcnt 0x0
+; GFX12-NEXT:    v_mad_co_u64_u32 v[6:7], null, 0xfffffc88, v3, v[2:3]
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_sub_nc_u32_e32 v1, v5, v1
+; GFX12-NEXT:    v_sub_nc_u32_e32 v2, v7, v3
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_xor_b32_e32 v0, v4, v6
+; GFX12-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX12-NEXT:    s_setpc_b64 s[30:31]
+  %4 = load i64, ptr addrspace(1) %1, align 8
----------------
vikramRH wrote:

done

https://github.com/llvm/llvm-project/pull/119509