[llvm] [RISC-V] Base scheduling model for tt-ascalon-d8 (PR #120160)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 16 22:19:31 PST 2024
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@@ -0,0 +1,333 @@
+//=- RISCVSchedTTAscalonD8.td - TT Ascalon D8 Sched Defs -----*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+
+def TTAscalonD8Model : SchedMachineModel {
+ let IssueWidth = 8; // 8-way decode and dispatch
+ let MicroOpBufferSize = 256; // 256 micro-op re-order buffer
+ let LoadLatency = 4; // Optimistic load latency
+ let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
+
+ // Enable partial & runtime unrolling.
+ let LoopMicroOpBufferSize = 16;
+
+ let CompleteModel = 0;
+
+ // TODO supported, but haven't added scheduling info yet
+ let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
+ HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
+ HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
+ HasStdExtZkr, HasVInstructions, HasVInstructionsI64];
+}
+
+let SchedModel = TTAscalonD8Model in {
+
+//===----------------------------------------------------------------------===//
+// Define each kind of processor resource and number available.
+
+let BufferSize = 16 in {
+ def AscalonLS : ProcResource<3>;
+ def AscalonFXA : ProcResource<1>; // ALU, FP/VEC -> INT, MUL, DIV, CSR
+ def AscalonFXB : ProcResource<1>; // ALU, INT -> FP/VEC
+ def AscalonFXC : ProcResource<2>; // ALU, BR
+ def AscalonFXD : ProcResource<2>; // ALU
+ def AscalonFP : ProcResource<2>;
+ def AscalonV : ProcResource<2>;
----------------
wangpc-pp wrote:
Vector units are not used. You may add it when adding vector scheduling support.
https://github.com/llvm/llvm-project/pull/120160
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