[llvm] [NVPTX] Generalize and extend upsizing when lowering 8/16-bit-element vector loads/stores (PR #119622)

[Artem Belevich via llvm-commits]

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@@ -1576,8 +1583,9 @@ bool NVPTXDAGToDAGISel::tryLDGLDU(SDNode *N) {
       EltVT = OrigType;
       NumElts /= 2;
     } else if (OrigType == MVT::v4i8) {
+      assert(NumElts % 4 == 0 && "NumElts must be a multuple of 4");
       EltVT = OrigType;
-      NumElts = 1;
+      NumElts /= 4;
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Artem-B wrote:

LGTM.

https://github.com/llvm/llvm-project/pull/119622