[llvm] [RISC-V] Base scheduling model for tt-ascalon-d8 (PR #120160)

[Craig Topper via llvm-commits]

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@@ -54,6 +54,7 @@ include "RISCVSchedSyntacoreSCR1.td"
 include "RISCVSchedSyntacoreSCR345.td"
 include "RISCVSchedSyntacoreSCR7.td"
 include "RISCVSchedXiangShanNanHu.td"
+include "RISCVSchedTTAscalonD8.td"
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topperc wrote:

Alphabetize?

https://github.com/llvm/llvm-project/pull/120160