[llvm] cedc9bf - [RISCV] Add MIPSP8700 RISCVProcFamilyEnum (#120073)

[via llvm-commits]

Author: Djordje Todorovic
Date: 2024-12-16T16:06:53+01:00
New Revision: cedc9bf94a6c40561c4ecb292126352d49c9129b

URL: https://github.com/llvm/llvm-project/commit/cedc9bf94a6c40561c4ecb292126352d49c9129b
DIFF: https://github.com/llvm/llvm-project/commit/cedc9bf94a6c40561c4ecb292126352d49c9129b.diff

LOG: [RISCV] Add MIPSP8700 RISCVProcFamilyEnum (#120073)

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVFeatures.td
    llvm/lib/Target/RISCV/RISCVSubtarget.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 15dc0bc0ce68f6..5fc7e4eef3c051 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1384,7 +1384,7 @@ def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()"
 def NoConditionalMoveFusion  : Predicate<"!Subtarget->hasConditionalMoveFusion()">;
 
 def TuneMIPSP8700
-    : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "Others",
+    : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700",
                        "MIPS p8700 processor">;
 
 def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",

diff  --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index d3dddfee84450b..096d696c71f8f5 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -82,6 +82,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
     Others,
     SiFive7,
     VentanaVeyron,
+    MIPSP8700,
   };
   // clang-format on
 private: