[llvm] [RISCV] Add ISAInfoTest tests for a few XQCI extensions (PR #120060)

[Sudharsan Veeravalli via llvm-commits]

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/120060

>From 016b533a96fddfed65695a43faabd83a58af9e16 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Mon, 16 Dec 2024 15:08:32 +0530
Subject: [PATCH 1/2] [RISCV] Add ISAInfoTest for a few XQCI extensions

Missed out adding rv32 only support test checks for a few of the
extensions.
---
 llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index bef3f571b174d3..6bad23e1c2409e 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -662,6 +662,21 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
     EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
               "'xqcia' is only supported for 'rv32'");
   }
+
+  for (StringRef Input : {"rv64i_xqcicsr0p2"}) {
+    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+              "'xqcicsr' is only supported for 'rv32'");
+  }
+
+  for (StringRef Input : {"rv64i_xqcilsm0p2"}) {
+    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+              "'xqcilsm' is only supported for 'rv32'");
+  }
+
+  for (StringRef Input : {"rv64i_xqcics0p2"}) {
+    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+              "'xqcics' is only supported for 'rv32'");
+  }
 }
 
 TEST(ParseArchString, MissingDepency) {

>From 40e0d2ee0a3ad4d1bfb05e7b58d208755d01af96 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Mon, 16 Dec 2024 18:43:21 +0530
Subject: [PATCH 2/2] Add single for loop

---
 .../TargetParser/RISCVISAInfoTest.cpp         | 29 ++++---------------
 1 file changed, 6 insertions(+), 23 deletions(-)

diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 6bad23e1c2409e..ed334f00eb93a4 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -653,29 +653,12 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
               "'xwchc' and 'zcb' extensions are incompatible");
   }
 
-  for (StringRef Input : {"rv64i_xqcisls0p2"}) {
-    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
-              "'xqcisls' is only supported for 'rv32'");
-  }
-
-  for (StringRef Input : {"rv64i_xqcia0p2"}) {
-    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
-              "'xqcia' is only supported for 'rv32'");
-  }
-
-  for (StringRef Input : {"rv64i_xqcicsr0p2"}) {
-    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
-              "'xqcicsr' is only supported for 'rv32'");
-  }
-
-  for (StringRef Input : {"rv64i_xqcilsm0p2"}) {
-    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
-              "'xqcilsm' is only supported for 'rv32'");
-  }
-
-  for (StringRef Input : {"rv64i_xqcics0p2"}) {
-    EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
-              "'xqcics' is only supported for 'rv32'");
+  for (StringRef Input :
+       {"rv64i_xqcisls0p2", "rv64i_xqcia0p2", "rv64i_xqcicsr0p2",
+        "rv64i_xqcilsm0p2", "rv64i_xqcics0p2"}) {
+    EXPECT_THAT(
+        toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+        ::testing::EndsWith(" is only supported for 'rv32'"));
   }
 }