[llvm] [RISCV] Add MIPSP8700 RISCVProcFamilyEnum (PR #120073)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Djordje Todorovic (djtodoro)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/120073.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+1-1) 
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (+1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index e770c39f42abfa..5f7ca3ac793079 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1494,7 +1494,7 @@ def HasConditionalMoveFusion : Predicate<"Subtarget->hasConditionalMoveFusion()"
 def NoConditionalMoveFusion  : Predicate<"!Subtarget->hasConditionalMoveFusion()">;
 
 def TuneMIPSP8700
-    : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "Others",
+    : SubtargetFeature<"mips-p8700", "RISCVProcFamily", "MIPSP8700",
                        "MIPS p8700 processor">;
 
 def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index f83125c35b388d..584b5a5e734f38 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -83,6 +83,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
     Others,
     SiFive7,
     VentanaVeyron,
+    MIPSP8700,
   };
   // clang-format on
 private:

``````````

</details>


https://github.com/llvm/llvm-project/pull/120073