[llvm] [AMDGPU][MC] Allow null where 128b or larger dst reg is expected (PR #115200)

[Jay Foad via llvm-commits]

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@@ -809,6 +809,10 @@ def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16,
   let BaseClassOrder = 32;
 }
 
+def SGPR_NULL128 : SIReg<"null">;
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jayfoad wrote:

Nit: is there a good reason why this definition is so different from SGPR_NULL64? Maybe they can be commoned up a bit?

https://github.com/llvm/llvm-project/pull/115200