[llvm] [RISCV] Add ISAInfoTest tests for a few XQCI extensions (PR #120060)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 16 01:42:02 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Sudharsan Veeravalli (svs-quic)
<details>
<summary>Changes</summary>
Missed out adding rv32 only support test checks for a few of the extensions.
---
Full diff: https://github.com/llvm/llvm-project/pull/120060.diff
1 Files Affected:
- (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+15)
``````````diff
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index bef3f571b174d3..6bad23e1c2409e 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -662,6 +662,21 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
"'xqcia' is only supported for 'rv32'");
}
+
+ for (StringRef Input : {"rv64i_xqcicsr0p2"}) {
+ EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+ "'xqcicsr' is only supported for 'rv32'");
+ }
+
+ for (StringRef Input : {"rv64i_xqcilsm0p2"}) {
+ EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+ "'xqcilsm' is only supported for 'rv32'");
+ }
+
+ for (StringRef Input : {"rv64i_xqcics0p2"}) {
+ EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+ "'xqcics' is only supported for 'rv32'");
+ }
}
TEST(ParseArchString, MissingDepency) {
``````````
</details>
https://github.com/llvm/llvm-project/pull/120060
More information about the llvm-commits
mailing list