[llvm] a35db28 - [NFC] Remove some unnecessary semicolons
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 16 00:49:04 PST 2024
Author: David Green
Date: 2024-12-16T08:48:57Z
New Revision: a35db2880a488b62a16f269972ad885fd58033f7
URL: https://github.com/llvm/llvm-project/commit/a35db2880a488b62a16f269972ad885fd58033f7
DIFF: https://github.com/llvm/llvm-project/commit/a35db2880a488b62a16f269972ad885fd58033f7.diff
LOG: [NFC] Remove some unnecessary semicolons
All inside LLVM_DEBUG, some of which have been cleaned up by adding block
scopes to allow them to format more nicely.
Added:
Modified:
llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
llvm/lib/CodeGen/BranchFolding.cpp
llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
llvm/lib/CodeGen/MachineCombiner.cpp
llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
llvm/lib/CodeGen/MachineOutliner.cpp
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/CodeGen/ModuloSchedule.cpp
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
index 9f8eb030a96c64..2c57f2b5aa029c 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
@@ -219,12 +219,13 @@ bool GIMatchTableExecutor::executeMatchTable(
assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
unsigned Opcode = State.MIs[InsnID]->getOpcode();
- DEBUG_WITH_TYPE(TgtExecutor::getName(),
- dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
- << "], ExpectedOpcode=" << Expected0;
- if (MatcherOpcode == GIM_CheckOpcodeIsEither) dbgs()
- << " || " << Expected1;
- dbgs() << ") // Got=" << Opcode << "\n";);
+ DEBUG_WITH_TYPE(TgtExecutor::getName(), {
+ dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
+ << "], ExpectedOpcode=" << Expected0;
+ if (MatcherOpcode == GIM_CheckOpcodeIsEither)
+ dbgs() << " || " << Expected1;
+ dbgs() << ") // Got=" << Opcode << "\n";
+ });
if (Opcode != Expected0 && Opcode != Expected1) {
if (handleReject() == RejectAndGiveUp)
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
index 61e88b161d94f1..0d2ff098a15e3d 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -70,7 +70,7 @@ class LegalizationArtifactCombiner {
// aext(trunc x) - > aext/copy/trunc x
Register TruncSrc;
if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
- LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
+ LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI);
if (MRI.getType(DstReg) == MRI.getType(TruncSrc))
replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs,
Observer);
@@ -136,7 +136,7 @@ class LegalizationArtifactCombiner {
if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
isConstantUnsupported(DstTy))
return false;
- LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
+ LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI);
LLT SrcTy = MRI.getType(SrcReg);
APInt MaskVal = APInt::getAllOnes(SrcTy.getScalarSizeInBits());
if (SextSrc && (DstTy != MRI.getType(SextSrc)))
@@ -207,7 +207,7 @@ class LegalizationArtifactCombiner {
LLT DstTy = MRI.getType(DstReg);
if (isInstUnsupported({TargetOpcode::G_SEXT_INREG, {DstTy}}))
return false;
- LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
+ LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI);
LLT SrcTy = MRI.getType(SrcReg);
uint64_t SizeInBits = SrcTy.getScalarSizeInBits();
if (DstTy != MRI.getType(TruncSrc))
@@ -360,7 +360,7 @@ class LegalizationArtifactCombiner {
LLT FoundRegTy = MRI.getType(FoundReg);
if (DstTy == FoundRegTy) {
LLVM_DEBUG(dbgs() << ".. Combine G_TRUNC(G_[S,Z,ANY]EXT/G_TRUNC...): "
- << MI;);
+ << MI);
replaceRegOrBuildCopy(DstReg, FoundReg, MRI, Builder, UpdatedDefs,
Observer);
@@ -392,7 +392,7 @@ class LegalizationArtifactCombiner {
// G_ANYEXT (G_IMPLICIT_DEF) -> G_IMPLICIT_DEF
if (!isInstLegal({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}))
return false;
- LLVM_DEBUG(dbgs() << ".. Combine G_ANYEXT(G_IMPLICIT_DEF): " << MI;);
+ LLVM_DEBUG(dbgs() << ".. Combine G_ANYEXT(G_IMPLICIT_DEF): " << MI);
auto Impl = Builder.buildUndef(DstTy);
replaceRegOrBuildCopy(DstReg, Impl.getReg(0), MRI, Builder, UpdatedDefs,
Observer);
@@ -402,7 +402,7 @@ class LegalizationArtifactCombiner {
// bits will be 0 for G_ZEXT and 0/1 for the G_SEXT.
if (isConstantUnsupported(DstTy))
return false;
- LLVM_DEBUG(dbgs() << ".. Combine G_[SZ]EXT(G_IMPLICIT_DEF): " << MI;);
+ LLVM_DEBUG(dbgs() << ".. Combine G_[SZ]EXT(G_IMPLICIT_DEF): " << MI);
auto Cnst = Builder.buildConstant(DstTy, 0);
replaceRegOrBuildCopy(DstReg, Cnst.getReg(0), MRI, Builder, UpdatedDefs,
Observer);
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index f8de13650680a8..1dd7cccd90119d 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -891,19 +891,21 @@ bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB,
unsigned MinCommonTailLength) {
bool MadeChange = false;
- LLVM_DEBUG(
- dbgs() << "\nTryTailMergeBlocks: ";
- for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i) dbgs()
- << printMBBReference(*MergePotentials[i].getBlock())
- << (i == e - 1 ? "" : ", ");
- dbgs() << "\n"; if (SuccBB) {
- dbgs() << " with successor " << printMBBReference(*SuccBB) << '\n';
- if (PredBB)
- dbgs() << " which has fall-through from "
- << printMBBReference(*PredBB) << "\n";
- } dbgs() << "Looking for common tails of at least "
- << MinCommonTailLength << " instruction"
- << (MinCommonTailLength == 1 ? "" : "s") << '\n';);
+ LLVM_DEBUG({
+ dbgs() << "\nTryTailMergeBlocks: ";
+ for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i)
+ dbgs() << printMBBReference(*MergePotentials[i].getBlock())
+ << (i == e - 1 ? "" : ", ");
+ dbgs() << "\n";
+ if (SuccBB) {
+ dbgs() << " with successor " << printMBBReference(*SuccBB) << '\n';
+ if (PredBB)
+ dbgs() << " which has fall-through from " << printMBBReference(*PredBB)
+ << "\n";
+ }
+ dbgs() << "Looking for common tails of at least " << MinCommonTailLength
+ << " instruction" << (MinCommonTailLength == 1 ? "" : "s") << '\n';
+ });
// Sort by hash value so that blocks with identical end sequences sort
// together.
diff --git a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
index cfb4ae85aa4f77..0ac4a8a0aa910b 100644
--- a/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp
@@ -163,7 +163,7 @@ MachineInstr *GISelCSEInfo::getMachineInstrIfExists(FoldingSetNodeID &ID,
void *&InsertPos) {
handleRecordedInsts();
if (auto *Inst = getNodeIfExists(ID, MBB, InsertPos)) {
- LLVM_DEBUG(dbgs() << "CSEInfo::Found Instr " << *Inst->MI;);
+ LLVM_DEBUG(dbgs() << "CSEInfo::Found Instr " << *Inst->MI);
return const_cast<MachineInstr *>(Inst->MI);
}
return nullptr;
@@ -313,11 +313,11 @@ Error GISelCSEInfo::verify() {
}
void GISelCSEInfo::print() {
- LLVM_DEBUG(for (auto &It
- : OpcodeHitTable) {
- dbgs() << "CSEInfo::CSE Hit for Opc " << It.first << " : " << It.second
- << "\n";
- };);
+ LLVM_DEBUG({
+ for (auto &It : OpcodeHitTable)
+ dbgs() << "CSEInfo::CSE Hit for Opc " << It.first << " : " << It.second
+ << "\n";
+ });
}
/// -----------------------------------------
// ---- Profiling methods for FoldingSetNode --- //
diff --git a/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp b/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
index 21b849244d9be2..4be708a6abfad6 100644
--- a/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
+++ b/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
@@ -271,15 +271,14 @@ static bool rescheduleCanonically(unsigned &PseudoIdempotentInstCount,
continue;
LLVM_DEBUG(
- dbgs() << "Rescheduling Multi-Use Instructions Lexographically.";);
+ dbgs() << "Rescheduling Multi-Use Instructions Lexographically.");
Changed |= rescheduleLexographically(
MultiUsers[E.second], MBB,
[&]() -> MachineBasicBlock::iterator { return UseI; });
}
PseudoIdempotentInstCount = PseudoIdempotentInstructions.size();
- LLVM_DEBUG(
- dbgs() << "Rescheduling Idempotent Instructions Lexographically.";);
+ LLVM_DEBUG(dbgs() << "Rescheduling Idempotent Instructions Lexographically.");
Changed |= rescheduleLexographically(
PseudoIdempotentInstructions, MBB,
[&]() -> MachineBasicBlock::iterator { return MBB->begin(); });
@@ -365,7 +364,7 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB,
bool Changed = false;
- LLVM_DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n";);
+ LLVM_DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n");
LLVM_DEBUG(dbgs() << "MBB Before Canonical Copy Propagation:\n";
MBB->dump(););
@@ -384,7 +383,7 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB,
Changed |= doDefKillClear(MBB);
LLVM_DEBUG(dbgs() << "Updated MachineBasicBlock:\n"; MBB->dump();
- dbgs() << "\n";);
+ dbgs() << "\n");
LLVM_DEBUG(
dbgs() << "\n\n================================================\n\n");
return Changed;
diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp
index 141cc1f35d66c3..b8d59214a6ec32 100644
--- a/llvm/lib/CodeGen/MachineCombiner.cpp
+++ b/llvm/lib/CodeGen/MachineCombiner.cpp
@@ -399,7 +399,7 @@ bool MachineCombiner::improvesCriticalPathLen(
<< RootSlack << " SlackIsAccurate=" << SlackIsAccurate
<< "\n\tNewRootDepth + NewRootLatency = " << NewCycleCount
<< "\n\tRootDepth + RootLatency + RootSlack = "
- << OldCycleCount;);
+ << OldCycleCount);
LLVM_DEBUG(NewCycleCount <= OldCycleCount
? dbgs() << "\n\t It IMPROVES PathLen because"
: dbgs() << "\n\t It DOES NOT improve PathLen because");
@@ -452,7 +452,7 @@ bool MachineCombiner::preservesResourceLen(
LLVM_DEBUG(dbgs() << "\t\tResource length before replacement: "
<< ResLenBeforeCombine
- << " and after: " << ResLenAfterCombine << "\n";);
+ << " and after: " << ResLenAfterCombine << "\n");
LLVM_DEBUG(
ResLenAfterCombine <=
ResLenBeforeCombine + TII->getExtendResourceLenLimit()
diff --git a/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp b/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
index 6399e8a9523685..8827a8327670a8 100644
--- a/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
+++ b/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp
@@ -189,7 +189,7 @@ bool MachineLateInstrsCleanup::processBlock(MachineBasicBlock *MBB) {
})) {
MBBDefs[Reg] = DefMI;
LLVM_DEBUG(dbgs() << "Reusable instruction from pred(s): in "
- << printMBBReference(*MBB) << ": " << *DefMI;);
+ << printMBBReference(*MBB) << ": " << *DefMI);
}
}
@@ -212,7 +212,7 @@ bool MachineLateInstrsCleanup::processBlock(MachineBasicBlock *MBB) {
// Check for an earlier identical and reusable instruction.
if (IsCandidate && MBBDefs.hasIdentical(DefedReg, &MI)) {
LLVM_DEBUG(dbgs() << "Removing redundant instruction in "
- << printMBBReference(*MBB) << ": " << MI;);
+ << printMBBReference(*MBB) << ": " << MI);
removeRedundantDef(&MI);
Changed = true;
continue;
@@ -232,7 +232,7 @@ bool MachineLateInstrsCleanup::processBlock(MachineBasicBlock *MBB) {
// Record this MI for potential later reuse.
if (IsCandidate) {
LLVM_DEBUG(dbgs() << "Found interesting instruction in "
- << printMBBReference(*MBB) << ": " << MI;);
+ << printMBBReference(*MBB) << ": " << MI);
MBBDefs[DefedReg] = &MI;
assert(!MBBKills.count(DefedReg) && "Should already have been removed.");
}
diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp
index 19a96e33163e36..4c5489434c69bb 100644
--- a/llvm/lib/CodeGen/MachineOutliner.cpp
+++ b/llvm/lib/CodeGen/MachineOutliner.cpp
@@ -1182,7 +1182,7 @@ bool MachineOutliner::outline(
}
}
- LLVM_DEBUG(dbgs() << "OutlinedSomething = " << OutlinedSomething << "\n";);
+ LLVM_DEBUG(dbgs() << "OutlinedSomething = " << OutlinedSomething << "\n");
return OutlinedSomething;
}
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 7a10bd39e2695d..f4b5f7c02b7153 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -3336,15 +3336,15 @@ void SwingSchedulerDAG::checkValidNodeOrder(const NodeSetType &Circuits) const {
bool InCircuit = llvm::any_of(
Circuits, [SU](const NodeSet &Circuit) { return Circuit.count(SU); });
if (InCircuit)
- LLVM_DEBUG(dbgs() << "In a circuit, predecessor ";);
+ LLVM_DEBUG(dbgs() << "In a circuit, predecessor ");
else {
Valid = false;
NumNodeOrderIssues++;
- LLVM_DEBUG(dbgs() << "Predecessor ";);
+ LLVM_DEBUG(dbgs() << "Predecessor ");
}
LLVM_DEBUG(dbgs() << Pred->NodeNum << " and successor " << Succ->NodeNum
<< " are scheduled before node " << SU->NodeNum
- << "\n";);
+ << "\n");
}
}
@@ -3573,7 +3573,7 @@ bool ResourceManager::canReserveResources(SUnit &SU, int Cycle) {
bool Result = !isOverbooked();
unreserveResources(SCDesc, Cycle);
- LLVM_DEBUG(if (SwpDebugResource) dbgs() << "return " << Result << "\n\n";);
+ LLVM_DEBUG(if (SwpDebugResource) dbgs() << "return " << Result << "\n\n");
return Result;
}
diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp
index 99c82bc3a2660a..414c8cd71809db 100644
--- a/llvm/lib/CodeGen/ModuloSchedule.cpp
+++ b/llvm/lib/CodeGen/ModuloSchedule.cpp
@@ -2693,8 +2693,7 @@ void ModuloScheduleExpanderMVE::expand() {
/// Check if ModuloScheduleExpanderMVE can be applied to L
bool ModuloScheduleExpanderMVE::canApply(MachineLoop &L) {
if (!L.getExitBlock()) {
- LLVM_DEBUG(
- dbgs() << "Can not apply MVE expander: No single exit block.\n";);
+ LLVM_DEBUG(dbgs() << "Can not apply MVE expander: No single exit block.\n");
return false;
}
@@ -2711,9 +2710,8 @@ bool ModuloScheduleExpanderMVE::canApply(MachineLoop &L) {
if (MO.isReg())
for (MachineInstr &Ref : MRI.use_instructions(MO.getReg()))
if (Ref.getParent() != BB || Ref.isPHI()) {
- LLVM_DEBUG(dbgs()
- << "Can not apply MVE expander: A phi result is "
- "referenced outside of the loop or by phi.\n";);
+ LLVM_DEBUG(dbgs() << "Can not apply MVE expander: A phi result is "
+ "referenced outside of the loop or by phi.\n");
return false;
}
@@ -2726,12 +2724,12 @@ bool ModuloScheduleExpanderMVE::canApply(MachineLoop &L) {
MRI.getVRegDef(LoopVal)->getParent() != BB) {
LLVM_DEBUG(
dbgs() << "Can not apply MVE expander: A phi source value coming "
- "from the loop is not defined in the loop.\n";);
+ "from the loop is not defined in the loop.\n");
return false;
}
if (UsedByPhi.count(LoopVal)) {
LLVM_DEBUG(dbgs() << "Can not apply MVE expander: A value defined in the "
- "loop is referenced by two or more phis.\n";);
+ "loop is referenced by two or more phis.\n");
return false;
}
UsedByPhi.insert(LoopVal);
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index b1d74437848145..6d3b3f34e8cabc 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -908,7 +908,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AAResults *AA,
BarrierChain = SU;
LLVM_DEBUG(dbgs() << "Global memory object and new barrier chain: SU("
- << BarrierChain->NodeNum << ").\n";);
+ << BarrierChain->NodeNum << ").\n");
// Add dependencies against everything below it and clear maps.
addBarrierChain(Stores);
@@ -929,7 +929,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AAResults *AA,
FPExceptions.insert(SU, UnknownValue);
if (FPExceptions.size() >= HugeRegion) {
- LLVM_DEBUG(dbgs() << "Reducing FPExceptions map.\n";);
+ LLVM_DEBUG(dbgs() << "Reducing FPExceptions map.\n");
Value2SUsMap empty;
reduceHugeMemNodeMaps(FPExceptions, empty, getReductionSize());
}
@@ -1012,12 +1012,11 @@ void ScheduleDAGInstrs::buildSchedGraph(AAResults *AA,
// Reduce maps if they grow huge.
if (Stores.size() + Loads.size() >= HugeRegion) {
- LLVM_DEBUG(dbgs() << "Reducing Stores and Loads maps.\n";);
+ LLVM_DEBUG(dbgs() << "Reducing Stores and Loads maps.\n");
reduceHugeMemNodeMaps(Stores, Loads, getReductionSize());
}
if (NonAliasStores.size() + NonAliasLoads.size() >= HugeRegion) {
- LLVM_DEBUG(
- dbgs() << "Reducing NonAliasStores and NonAliasLoads maps.\n";);
+ LLVM_DEBUG(dbgs() << "Reducing NonAliasStores and NonAliasLoads maps.\n");
reduceHugeMemNodeMaps(NonAliasStores, NonAliasLoads, getReductionSize());
}
}
@@ -1090,11 +1089,11 @@ void ScheduleDAGInstrs::reduceHugeMemNodeMaps(Value2SUsMap &stores,
BarrierChain->addPredBarrier(newBarrierChain);
BarrierChain = newBarrierChain;
LLVM_DEBUG(dbgs() << "Inserting new barrier chain: SU("
- << BarrierChain->NodeNum << ").\n";);
+ << BarrierChain->NodeNum << ").\n");
}
else
LLVM_DEBUG(dbgs() << "Keeping old barrier chain: SU("
- << BarrierChain->NodeNum << ").\n";);
+ << BarrierChain->NodeNum << ").\n");
}
else
BarrierChain = newBarrierChain;
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 2480a94546c592..ec5b058da29710 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1229,7 +1229,7 @@ void FastISel::handleDbgInfo(const Instruction *II) {
}
if (!Res)
- LLVM_DEBUG(dbgs() << "Dropping debug-info for " << DVR << "\n";);
+ LLVM_DEBUG(dbgs() << "Dropping debug-info for " << DVR << "\n");
}
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 3000dfda1bea03..35aa7b87bc3b7f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -4269,11 +4269,12 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
CurDAG->setNodeMemRefs(Res, FilteredMemRefs);
}
- LLVM_DEBUG(if (!MatchedMemRefs.empty() && Res->memoperands_empty()) dbgs()
- << " Dropping mem operands\n";
- dbgs() << " " << (IsMorphNodeTo ? "Morphed" : "Created")
- << " node: ";
- Res->dump(CurDAG););
+ LLVM_DEBUG({
+ if (!MatchedMemRefs.empty() && Res->memoperands_empty())
+ dbgs() << " Dropping mem operands\n";
+ dbgs() << " " << (IsMorphNodeTo ? "Morphed" : "Created") << " node: ";
+ Res->dump(CurDAG);
+ });
// If this was a MorphNodeTo then we're completely done!
if (IsMorphNodeTo) {
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 41e0214dab6c73..a86ee5a6b64d27 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -12809,9 +12809,10 @@ SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
}
// Final check before we try to actually produce a shuffle.
- LLVM_DEBUG(for (auto Src
- : Sources)
- assert(Src.ShuffleVec.getValueType() == ShuffleVT););
+ LLVM_DEBUG({
+ for (auto Src : Sources)
+ assert(Src.ShuffleVec.getValueType() == ShuffleVT);
+ });
// The stars all align, our next step is to produce the mask for the shuffle.
SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
@@ -15065,8 +15066,10 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0);
++i;
}
- LLVM_DEBUG(if (i < NumElts) dbgs()
- << "Creating nodes for the other vector elements:\n";);
+ LLVM_DEBUG({
+ if (i < NumElts)
+ dbgs() << "Creating nodes for the other vector elements:\n";
+ });
for (; i < NumElts; ++i) {
SDValue V = Op.getOperand(i);
if (V.isUndef())
diff --git a/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp b/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
index d1a943d91c0644..174438c1863dda 100644
--- a/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
+++ b/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
@@ -240,13 +240,13 @@ void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd,
if (Chains.count(Ra)) {
if (Rd != Ra) {
LLVM_DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI)
- << " to " << printReg(Rd, TRI) << '\n';);
+ << " to " << printReg(Rd, TRI) << '\n');
Chains.remove(Ra);
Chains.insert(Rd);
}
} else {
LLVM_DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI)
- << '\n';);
+ << '\n');
Chains.insert(Rd);
}
@@ -271,7 +271,7 @@ void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd,
assert(edge != G.invalidEdgeId() &&
"PBQP error ! The edge should exist !");
- LLVM_DEBUG(dbgs() << "Refining constraint !\n";);
+ LLVM_DEBUG(dbgs() << "Refining constraint !\n");
if (G.getEdgeNode1Id(edge) == node2) {
std::swap(node1, node2);
@@ -333,7 +333,7 @@ void A57ChainingConstraint::apply(PBQPRAGraph &G) {
SmallVector<unsigned, 8> toDel;
if(regJustKilledBefore(LIs, r, MI)) {
LLVM_DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at ";
- MI.print(dbgs()););
+ MI.print(dbgs()));
toDel.push_back(r);
}
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 595bb6e73f453c..2b20154042fe29 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8356,9 +8356,10 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
}
// Final check before we try to actually produce a shuffle.
- LLVM_DEBUG(for (auto Src
- : Sources)
- assert(Src.ShuffleVec.getValueType() == ShuffleVT););
+ LLVM_DEBUG({
+ for (auto Src : Sources)
+ assert(Src.ShuffleVec.getValueType() == ShuffleVT);
+ });
// The stars all align, our next step is to produce the mask for the shuffle.
SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
diff --git a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
index 209a3a0a272104..1d68185d916f23 100644
--- a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
+++ b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
@@ -226,7 +226,7 @@ bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) {
// IT blocks are limited to one conditional op if -arm-restrict-it
// is set: skip the loop
if (!restrictIT) {
- LLVM_DEBUG(dbgs() << "Allowing complex IT block\n";);
+ LLVM_DEBUG(dbgs() << "Allowing complex IT block\n");
// Branches, including tricky ones like LDM_RET, need to end an IT
// block so check the instruction we just put in the block.
for (; MBBI != E && Pos &&
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