[llvm] [GlobalSel][NFC] Remove LLT initializers taking scalar sizes (PR #119725)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 16 00:22:20 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-tablegen
Author: Tim Gymnich (tgymnich)
<details>
<summary>Changes</summary>
Remove initializers taking a scalar size in favor of initializers taking a LLT. This avoids dropping additional type information that may be included in LLT in the future.
progresses on #<!-- -->119667
---
Patch is 121.16 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/119725.diff
36 Files Affected:
- (modified) llvm/include/llvm/CodeGen/MachineFunction.h (+6-6)
- (modified) llvm/include/llvm/CodeGenTypes/LowLevelType.h (-37)
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (+5-8)
- (modified) llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp (+7-9)
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp (+4-2)
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+40-32)
- (modified) llvm/lib/CodeGen/GlobalISel/Utils.cpp (+3-4)
- (modified) llvm/lib/CodeGen/LowLevelTypeUtils.cpp (+3-2)
- (modified) llvm/lib/CodeGen/MachineOperand.cpp (+6-4)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp (+26-25)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp (+38-37)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp (+7-6)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp (+2-2)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp (+26-23)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp (+2-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (+5-4)
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+61-57)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (+7-5)
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+2-2)
- (modified) llvm/lib/Target/Mips/MipsLegalizerInfo.cpp (+4-4)
- (modified) llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp (+4-4)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (+11-13)
- (modified) llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp (+14-15)
- (modified) llvm/unittests/CodeGen/GlobalISel/CSETest.cpp (+6-6)
- (modified) llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp (+64-48)
- (modified) llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp (+2-2)
- (modified) llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp (+47-33)
- (modified) llvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp (+46-41)
- (modified) llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp (+2-2)
- (modified) llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp (+18-14)
- (modified) llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp (+3-3)
- (modified) llvm/unittests/CodeGen/LowLevelTypeTest.cpp (+73-64)
- (modified) llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp (+6-4)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
index 547cc26eda2295..5fb397b99e0d77 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -1063,12 +1063,12 @@ class LLVM_ABI MachineFunction {
int64_t Offset, LLT Ty);
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
int64_t Offset, LocationSize Size) {
- return getMachineMemOperand(
- MMO, Offset,
- !Size.hasValue() ? LLT()
- : Size.isScalable()
- ? LLT::scalable_vector(1, 8 * Size.getValue().getKnownMinValue())
- : LLT::scalar(8 * Size.getValue().getKnownMinValue()));
+ if (!Size.hasValue())
+ return getMachineMemOperand(MMO, Offset, LLT());
+
+ ElementCount EC = ElementCount::get(1, Size.isScalable());
+ LLT Ty = LLT::scalar(8 * Size.getValue().getKnownMinValue());
+ return getMachineMemOperand(MMO, Offset, LLT::scalarOrVector(EC, Ty));
}
MachineMemOperand *getMachineMemOperand(const MachineMemOperand *MMO,
int64_t Offset, uint64_t Size) {
diff --git a/llvm/include/llvm/CodeGenTypes/LowLevelType.h b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
index 62ee28cfac99c5..f139800025541d 100644
--- a/llvm/include/llvm/CodeGenTypes/LowLevelType.h
+++ b/llvm/include/llvm/CodeGenTypes/LowLevelType.h
@@ -60,13 +60,6 @@ class LLT {
ElementCount::getFixed(0), SizeInBits, AddressSpace};
}
- /// Get a low-level vector of some number of elements and element width.
- static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits) {
- assert(!EC.isScalar() && "invalid number of vector elements");
- return LLT{/*isPointer=*/false, /*isVector=*/true, /*isScalar=*/false,
- EC, ScalarSizeInBits, /*AddressSpace=*/0};
- }
-
/// Get a low-level vector of some number of elements and element type.
static constexpr LLT vector(ElementCount EC, LLT ScalarTy) {
assert(!EC.isScalar() && "invalid number of vector elements");
@@ -95,26 +88,12 @@ class LLT {
return scalar(64);
}
- /// Get a low-level fixed-width vector of some number of elements and element
- /// width.
- static constexpr LLT fixed_vector(unsigned NumElements,
- unsigned ScalarSizeInBits) {
- return vector(ElementCount::getFixed(NumElements), ScalarSizeInBits);
- }
-
/// Get a low-level fixed-width vector of some number of elements and element
/// type.
static constexpr LLT fixed_vector(unsigned NumElements, LLT ScalarTy) {
return vector(ElementCount::getFixed(NumElements), ScalarTy);
}
- /// Get a low-level scalable vector of some number of elements and element
- /// width.
- static constexpr LLT scalable_vector(unsigned MinNumElements,
- unsigned ScalarSizeInBits) {
- return vector(ElementCount::getScalable(MinNumElements), ScalarSizeInBits);
- }
-
/// Get a low-level scalable vector of some number of elements and element
/// type.
static constexpr LLT scalable_vector(unsigned MinNumElements, LLT ScalarTy) {
@@ -125,12 +104,6 @@ class LLT {
return EC.isScalar() ? ScalarTy : LLT::vector(EC, ScalarTy);
}
- static constexpr LLT scalarOrVector(ElementCount EC, uint64_t ScalarSize) {
- assert(ScalarSize <= std::numeric_limits<unsigned>::max() &&
- "Not enough bits in LLT to represent size");
- return scalarOrVector(EC, LLT::scalar(static_cast<unsigned>(ScalarSize)));
- }
-
explicit constexpr LLT(bool isPointer, bool isVector, bool isScalar,
ElementCount EC, uint64_t SizeInBits,
unsigned AddressSpace)
@@ -215,16 +188,6 @@ class LLT {
return isVector() ? LLT::vector(getElementCount(), NewEltTy) : NewEltTy;
}
- /// If this type is a vector, return a vector with the same number of elements
- /// but the new element size. Otherwise, return the new element type. Invalid
- /// for pointer types. For pointer types, use changeElementType.
- constexpr LLT changeElementSize(unsigned NewEltSize) const {
- assert(!isPointerOrPointerVector() &&
- "invalid to directly change element size for pointers");
- return isVector() ? LLT::vector(getElementCount(), NewEltSize)
- : LLT::scalar(NewEltSize);
- }
-
/// Return a vector or scalar with the same element type and the new element
/// count.
constexpr LLT changeElementCount(ElementCount EC) const {
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index a2737995446526..d53de6e6db0754 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -2580,7 +2580,7 @@ static LLT getMidVTForTruncRightShiftCombine(LLT ShiftTy, LLT TruncTy) {
// ShiftTy > 32 > TruncTy -> 32
if (ShiftSize > 32 && TruncSize < 32)
- return ShiftTy.changeElementSize(32);
+ return ShiftTy.changeElementType(LLT::scalar(32));
// TODO: We could also reduce to 16 bits, but that's more target-dependent.
// Some targets like it, some don't, some only like it under certain
@@ -5362,9 +5362,8 @@ MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) {
Q = MIB.buildLShr(Ty, Q, PostShift).getReg(0);
auto One = MIB.buildConstant(Ty, 1);
- auto IsOne = MIB.buildICmp(
- CmpInst::Predicate::ICMP_EQ,
- Ty.isScalar() ? LLT::scalar(1) : Ty.changeElementSize(1), RHS, One);
+ auto IsOne = MIB.buildICmp(CmpInst::Predicate::ICMP_EQ,
+ Ty.changeElementType(LLT::scalar(1)), RHS, One);
return MIB.buildSelect(Ty, IsOne, LHS, Q);
}
@@ -5404,8 +5403,7 @@ bool CombinerHelper::matchUDivByConst(MachineInstr &MI) {
return false;
if (!isLegalOrBeforeLegalizer(
{TargetOpcode::G_ICMP,
- {DstTy.isVector() ? DstTy.changeElementSize(1) : LLT::scalar(1),
- DstTy}}))
+ {DstTy.changeElementType(LLT::scalar(1)), DstTy}}))
return false;
}
@@ -5538,8 +5536,7 @@ void CombinerHelper::applySDivByPow2(MachineInstr &MI) {
Register RHS = SDiv.getReg(2);
LLT Ty = MRI.getType(Dst);
LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty);
- LLT CCVT =
- Ty.isVector() ? LLT::vector(Ty.getElementCount(), 1) : LLT::scalar(1);
+ LLT CCVT = Ty.changeElementType(LLT::scalar(1));
// Effectively we want to lower G_SDIV %lhs, %rhs, where %rhs is a power of 2,
// to the following version:
diff --git a/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp b/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
index 45b403bdd07658..93561b04150406 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp
@@ -343,12 +343,11 @@ LegacyLegalizerInfo::findVectorLegalAction(const InstrAspect &Aspect) const {
ScalarInVectorActions[OpcodeIdx][TypeIdx];
LLT IntermediateType;
- auto ElementSizeAndAction =
+ auto &&[ElementSize, Action1] =
findAction(ElemSizeVec, Aspect.Type.getScalarSizeInBits());
- IntermediateType = LLT::fixed_vector(Aspect.Type.getNumElements(),
- ElementSizeAndAction.first);
- if (ElementSizeAndAction.second != Legal)
- return {ElementSizeAndAction.second, IntermediateType};
+ IntermediateType = Aspect.Type.changeElementType(LLT::scalar(ElementSize));
+ if (Action1 != Legal)
+ return {Action1, IntermediateType};
auto i = NumElements2Actions[OpcodeIdx].find(
IntermediateType.getScalarSizeInBits());
@@ -356,11 +355,10 @@ LegacyLegalizerInfo::findVectorLegalAction(const InstrAspect &Aspect) const {
return {NotFound, IntermediateType};
}
const SizeAndActionsVec &NumElementsVec = (*i).second[TypeIdx];
- auto NumElementsAndAction =
+ auto &&[NumElements, Action2] =
findAction(NumElementsVec, IntermediateType.getNumElements());
- return {NumElementsAndAction.second,
- LLT::fixed_vector(NumElementsAndAction.first,
- IntermediateType.getScalarSizeInBits())};
+ return {Action2,
+ LLT::fixed_vector(NumElements, IntermediateType.getScalarType())};
}
unsigned LegacyLegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const {
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
index 25c1db91b05d8e..b718300537ee21 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
@@ -80,7 +80,8 @@ LegalizeMutation LegalizeMutations::widenScalarOrEltToNextPow2(unsigned TypeIdx,
const LLT Ty = Query.Types[TypeIdx];
unsigned NewEltSizeInBits =
std::max(1u << Log2_32_Ceil(Ty.getScalarSizeInBits()), Min);
- return std::make_pair(TypeIdx, Ty.changeElementSize(NewEltSizeInBits));
+ return std::make_pair(TypeIdx,
+ Ty.changeElementType(LLT::scalar(NewEltSizeInBits)));
};
}
@@ -90,7 +91,8 @@ LegalizeMutations::widenScalarOrEltToNextMultipleOf(unsigned TypeIdx,
return [=](const LegalityQuery &Query) {
const LLT Ty = Query.Types[TypeIdx];
unsigned NewEltSizeInBits = alignTo(Ty.getScalarSizeInBits(), Size);
- return std::make_pair(TypeIdx, Ty.changeElementSize(NewEltSizeInBits));
+ return std::make_pair(TypeIdx,
+ Ty.changeElementType(LLT::scalar(NewEltSizeInBits)));
};
}
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index f56be39838ba7d..d5ec612b19cbd1 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3081,9 +3081,8 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
LLT VecTy = MRI.getType(VecReg);
Observer.changingInstr(MI);
- widenScalarSrc(
- MI, LLT::vector(VecTy.getElementCount(), WideTy.getSizeInBits()), 1,
- TargetOpcode::G_ANYEXT);
+ widenScalarSrc(MI, VecTy.changeElementType(WideTy), 1,
+ TargetOpcode::G_ANYEXT);
widenScalarDst(MI, WideTy, 0);
Observer.changedInstr(MI);
@@ -3815,7 +3814,7 @@ LegalizerHelper::bitcastExtractSubvector(MachineInstr &MI, unsigned TypeIdx,
return UnableToLegalize;
Idx /= AdjustAmt;
- SrcTy = LLT::vector(SrcTyEC.divideCoefficientBy(AdjustAmt), AdjustAmt);
+ SrcTy = SrcTy.divide(AdjustAmt).changeElementType(LLT::scalar(AdjustAmt));
auto CastVec = MIRBuilder.buildBitcast(SrcTy, Src);
auto PromotedES = MIRBuilder.buildExtractSubvector(CastTy, CastVec, Idx);
MIRBuilder.buildBitcast(Dst, PromotedES);
@@ -3883,8 +3882,10 @@ LegalizerHelper::bitcastInsertSubvector(MachineInstr &MI, unsigned TypeIdx,
return UnableToLegalize;
Idx /= AdjustAmt;
- BigVecTy = LLT::vector(BigVecTyEC.divideCoefficientBy(AdjustAmt), AdjustAmt);
- SubVecTy = LLT::vector(SubVecTyEC.divideCoefficientBy(AdjustAmt), AdjustAmt);
+ BigVecTy =
+ BigVecTy.divide(AdjustAmt).changeElementType(LLT::scalar(AdjustAmt));
+ SubVecTy =
+ SubVecTy.divide(AdjustAmt).changeElementType(LLT::scalar(AdjustAmt));
auto CastBigVec = MIRBuilder.buildBitcast(BigVecTy, BigVec);
auto CastSubVec = MIRBuilder.buildBitcast(SubVecTy, SubVec);
auto PromotedIS =
@@ -4632,7 +4633,8 @@ Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy,
const DataLayout &DL = MIRBuilder.getDataLayout();
unsigned AS = MRI.getType(VecPtr).getAddressSpace();
unsigned IndexSizeInBits = DL.getIndexSize(AS) * 8;
- LLT IdxTy = MRI.getType(Index).changeElementSize(IndexSizeInBits);
+ LLT IdxTy =
+ MRI.getType(Index).changeElementType(LLT::scalar(IndexSizeInBits));
if (IdxTy != MRI.getType(Index))
Index = MIRBuilder.buildSExtOrTrunc(IdxTy, Index).getReg(0);
@@ -5348,8 +5350,8 @@ LegalizerHelper::fewerElementsBitcast(MachineInstr &MI, unsigned int TypeIdx,
auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
unsigned SrcScalSize = SrcTy.getScalarSizeInBits();
- LLT SrcNarrowTy =
- LLT::fixed_vector(NarrowTy.getSizeInBits() / SrcScalSize, SrcScalSize);
+ LLT SrcNarrowTy = LLT::fixed_vector(NarrowTy.getSizeInBits() / SrcScalSize,
+ SrcTy.getScalarType());
// Split the Src and Dst Reg into smaller registers
SmallVector<Register> SrcVRegs, BitcastVRegs;
@@ -6883,8 +6885,9 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI) {
// If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg);
auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0);
- auto ICmp = MIRBuilder.buildICmp(
- CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc);
+ auto ICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ,
+ SrcTy.changeElementType(LLT::scalar(1)),
+ SrcReg, ZeroSrc);
auto LenConst = MIRBuilder.buildConstant(DstTy, Len);
MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU);
MI.eraseFromParent();
@@ -6931,8 +6934,9 @@ LegalizerHelper::lowerBitCount(MachineInstr &MI) {
// zero.
auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg);
auto Zero = MIRBuilder.buildConstant(SrcTy, 0);
- auto ICmp = MIRBuilder.buildICmp(
- CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero);
+ auto ICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ,
+ DstTy.changeElementType(LLT::scalar(1)),
+ SrcReg, Zero);
auto LenConst = MIRBuilder.buildConstant(DstTy, Len);
MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU);
MI.eraseFromParent();
@@ -7177,7 +7181,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerEXT(MachineInstr &MI) {
// The step between extend is too large, split it by creating an intermediate
// extend instruction
if (SrcTyScalarSize * 2 < DstTyScalarSize) {
- LLT MidTy = SrcTy.changeElementSize(SrcTyScalarSize * 2);
+ LLT MidTy = SrcTy.changeElementType(LLT::scalar(SrcTyScalarSize * 2));
// If the destination type is illegal, split it into multiple statements
// zext x -> zext(merge(zext(unmerge), zext(unmerge)))
auto NewExt = MIRBuilder.buildInstr(MI.getOpcode(), {MidTy}, {Src});
@@ -7236,16 +7240,17 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerTRUNC(MachineInstr &MI) {
// Truncate the splits into intermediate narrower elements.
LLT InterTy;
if (DstTy.getScalarSizeInBits() * 2 < SrcTy.getScalarSizeInBits())
- InterTy = SplitSrcTy.changeElementSize(DstTy.getScalarSizeInBits() * 2);
+ InterTy = SplitSrcTy.changeElementType(
+ LLT::scalar(DstTy.getScalarSizeInBits() * 2));
else
- InterTy = SplitSrcTy.changeElementSize(DstTy.getScalarSizeInBits());
+ InterTy = SplitSrcTy.changeElementType(DstTy.getScalarType());
for (unsigned I = 0; I < SplitSrcs.size(); ++I) {
SplitSrcs[I] = MIRBuilder.buildTrunc(InterTy, SplitSrcs[I]).getReg(0);
}
// Combine the new truncates into one vector
auto Merge = MIRBuilder.buildMergeLikeInstr(
- DstTy.changeElementSize(InterTy.getScalarSizeInBits()), SplitSrcs);
+ DstTy.changeElementType(InterTy.getScalarType()), SplitSrcs);
// Truncate the new vector to the final result type
if (DstTy.getScalarSizeInBits() * 2 < SrcTy.getScalarSizeInBits())
@@ -7672,6 +7677,8 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
bool AreExactFloatBounds = !(MinStatus & APFloat::opStatus::opInexact) &&
!(MaxStatus & APFloat::opStatus::opInexact);
+ const LLT S1 = LLT::scalar(1);
+
// If the integer bounds are exactly representable as floats, emit a
// min+max+fptoi sequence. Otherwise we have to use a sequence of comparisons
// and selects.
@@ -7679,13 +7686,13 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
// Clamp Src by MinFloat from below. If Src is NaN the result is MinFloat.
auto MaxC = MIRBuilder.buildFConstant(SrcTy, MinFloat);
auto MaxP = MIRBuilder.buildFCmp(CmpInst::FCMP_ULT,
- SrcTy.changeElementSize(1), Src, MaxC);
+ SrcTy.changeElementType(S1), Src, MaxC);
auto Max = MIRBuilder.buildSelect(SrcTy, MaxP, Src, MaxC);
// Clamp by MaxFloat from above. NaN cannot occur.
auto MinC = MIRBuilder.buildFConstant(SrcTy, MaxFloat);
auto MinP =
- MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, SrcTy.changeElementSize(1), Max,
- MinC, MachineInstr::FmNoNans);
+ MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, SrcTy.changeElementType(S1),
+ Max, MinC, MachineInstr::FmNoNans);
auto Min =
MIRBuilder.buildSelect(SrcTy, MinP, Max, MinC, MachineInstr::FmNoNans);
// Convert clamped value to integer. In the unsigned case we're done,
@@ -7699,7 +7706,7 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
// Otherwise, select 0 if Src is NaN.
auto FpToInt = MIRBuilder.buildFPTOSI(DstTy, Min);
auto IsZero = MIRBuilder.buildFCmp(CmpInst::FCMP_UNO,
- DstTy.changeElementSize(1), Src, Src);
+ DstTy.changeElementType(S1), Src, Src);
MIRBuilder.buildSelect(Dst, IsZero, MIRBuilder.buildConstant(DstTy, 0),
FpToInt);
MI.eraseFromParent();
@@ -7715,13 +7722,13 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
// If Src ULT MinFloat, select MinInt. In particular, this also selects
// MinInt if Src is NaN.
auto ULT =
- MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, SrcTy.changeElementSize(1), Src,
+ MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, SrcTy.changeElementType(S1), Src,
MIRBuilder.buildFConstant(SrcTy, MinFloat));
auto Max = MIRBuilder.buildSelect(
DstTy, ULT, MIRBuilder.buildConstant(DstTy, MinInt), FpToInt);
// If Src OGT MaxFloat, select MaxInt.
auto OGT =
- MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, SrcTy.changeElementSize(1), Src,
+ MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, SrcTy.changeElementType(S1), Src,
MIRBuilder.buildFConstant(SrcTy, MaxFloat));
// In the unsigned case we are done, because we mapped NaN to MinInt, which
@@ -7737,7 +7744,7 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
auto Min = MIRBuilder.buildSelect(
DstTy, OGT, MIRBuilder.buildConstant(DstTy, MaxInt), Max);
auto IsZero = MIRBuilder.buildFCmp(CmpInst::FCMP_UNO,
- DstTy.changeElementSize(1), Src, Src);
+ DstTy.changeElementType(S1), Src, Src);
MIRBuilder.buildSelect(Dst, IsZero, MIRBuilder.buildConstant(DstTy, 0), Min);
MI.eraseFromParent();
return Legalized;
@@ -7900,7 +7907,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) {
auto [Dst, Src0, Src1] = MI.getFirst3Regs();
const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
- LLT CmpType = MRI.getType(Dst).changeElementSize(1);
+ LLT CmpType = MRI.getType(Dst).changeElementType(LLT::scalar(1));
auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
@@ -7915,7 +7922,7 @@ LegalizerHelper::lowerThreewayCompare(MachineInstr &MI) {
Register Dst = Cmp->getReg(0);
LLT DstTy = MRI.getType(Dst);
- LLT CmpTy = DstTy.changeElementSize(1);
+ LLT CmpTy = DstTy.changeElementType(LLT::scalar(1));
CmpInst::Predicate LTPredicate = Cmp->isSigned()
? CmpInst::Predicate::ICMP_SLT
@@ -8028,7 +8035,7 @@ LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
auto [DstReg, X] = MI.getFirst2Regs();
const unsigned Flags = MI.getFlags();
const LLT Ty = MRI.getType(DstReg);
- const LLT CondTy = Ty.changeElementSize(1);
+ const LLT CondTy = Ty.changeElementType(LLT::scalar(1));
// round(x) =>
// t = trunc(x);
@@ -8061,7 +8068,7 @@ LegalizerHelp...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/119725
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