[llvm] [RISCV][GISel] Lower G_SCMP and G_UCMP. (PR #119112)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 8 22:41:39 PST 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/119112
>From 5036d7f8a0d0bfffc8a65e12958f72769606d1dc Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 7 Dec 2024 20:33:17 -0800
Subject: [PATCH 1/2] [RISCV][GISel] Lower G_SCMP and G_UCMP.
---
.../Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 2 +
.../GlobalISel/legalizer-info-validation.mir | 9 ++-
.../legalizer/legalize-threeway-cmp-rv32.mir | 58 ++++++++++++++
.../legalizer/legalize-threeway-cmp-rv64.mir | 75 +++++++++++++++++++
4 files changed, 140 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv32.mir
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv64.mir
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 1199dabf3d1659..21bfb444a569d4 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -482,6 +482,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
.lower();
+ getActionDefinitionsBuilder({G_SCMP, G_UCMP}).lower();
+
getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
getActionDefinitionsBuilder({G_MEMCPY, G_MEMMOVE, G_MEMSET}).libcall();
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index fb28a260c82718..a27e2b80cd98fb 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -364,11 +364,12 @@
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_SCMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_UCMP (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_SELECT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv32.mir
new file mode 100644
index 00000000000000..5c3d7e5975f1fd
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv32.mir
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_ucmp_i32
+body: |
+ bb.1:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: test_ucmp_i32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[C2]], [[SELECT]]
+ ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_SCMP %0(s32), %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_scmp_i32
+alignment: 4
+body: |
+ bb.1:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: test_scmp_i32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[C]], [[C1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[COPY]](s32), [[COPY1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[C2]], [[SELECT]]
+ ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_SCMP %0(s32), %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv64.mir
new file mode 100644
index 00000000000000..ccade88ffae7c8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-threeway-cmp-rv64.mir
@@ -0,0 +1,75 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s
+
+---
+name: test_ucmp_i32
+body: |
+ bb.1:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: test_ucmp_i32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C1]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC2]], [[SELECT]]
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SELECT1]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[SEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %2:_(s64) = COPY $x10
+ %0:_(s32) = G_TRUNC %2(s64)
+ %3:_(s64) = COPY $x11
+ %1:_(s32) = G_TRUNC %3(s64)
+ %4:_(s32) = G_SCMP %0(s32), %1
+ %5:_(s64) = G_SEXT %4(s32)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: test_scmp_i32
+body: |
+ bb.1:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: test_scmp_i32
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[C1]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC]], [[TRUNC1]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(slt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s64), [[TRUNC2]], [[SELECT]]
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SELECT1]](s32)
+ ; CHECK-NEXT: $x10 = COPY [[SEXT]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %2:_(s64) = COPY $x10
+ %0:_(s32) = G_TRUNC %2(s64)
+ %3:_(s64) = COPY $x11
+ %1:_(s32) = G_TRUNC %3(s64)
+ %4:_(s32) = G_SCMP %0(s32), %1
+ %5:_(s64) = G_SEXT %4(s32)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
>From 796334710cd99ee2a7934273d8c017ba210a0df0 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sun, 8 Dec 2024 22:16:56 -0800
Subject: [PATCH 2/2] fixup! Add end to end tests.
---
llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll | 291 ++++++++++++++++
llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll | 370 +++++++++++++++++++++
2 files changed, 661 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll
create mode 100644 llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll
new file mode 100644
index 00000000000000..0f2b6281b6f88c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/scmp.ll
@@ -0,0 +1,291 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv32 -global-isel | FileCheck %s --check-prefix=RV32I
+; RUN: llc < %s -mtriple=riscv64 -global-isel | FileCheck %s --check-prefix=RV64I
+
+define i8 @scmp.8.8(i8 signext %x, i8 signext %y) nounwind {
+; RV32I-LABEL: scmp.8.8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: blt a1, a0, .LBB0_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: blt a2, a1, .LBB0_3
+; RV32I-NEXT: j .LBB0_4
+; RV32I-NEXT: .LBB0_2:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: bge a2, a1, .LBB0_4
+; RV32I-NEXT: .LBB0_3:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: .LBB0_4:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: scmp.8.8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: blt a1, a0, .LBB0_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: blt a2, a1, .LBB0_3
+; RV64I-NEXT: j .LBB0_4
+; RV64I-NEXT: .LBB0_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bge a2, a1, .LBB0_4
+; RV64I-NEXT: .LBB0_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB0_4:
+; RV64I-NEXT: ret
+ %1 = call i8 @llvm.scmp(i8 %x, i8 %y)
+ ret i8 %1
+}
+
+define i8 @scmp.8.16(i16 signext %x, i16 signext %y) nounwind {
+; RV32I-LABEL: scmp.8.16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: blt a1, a0, .LBB1_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: blt a2, a1, .LBB1_3
+; RV32I-NEXT: j .LBB1_4
+; RV32I-NEXT: .LBB1_2:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: bge a2, a1, .LBB1_4
+; RV32I-NEXT: .LBB1_3:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: .LBB1_4:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: scmp.8.16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: blt a1, a0, .LBB1_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: blt a2, a1, .LBB1_3
+; RV64I-NEXT: j .LBB1_4
+; RV64I-NEXT: .LBB1_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bge a2, a1, .LBB1_4
+; RV64I-NEXT: .LBB1_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB1_4:
+; RV64I-NEXT: ret
+ %1 = call i8 @llvm.scmp(i16 %x, i16 %y)
+ ret i8 %1
+}
+
+define i8 @scmp.8.32(i32 %x, i32 %y) nounwind {
+; RV32I-LABEL: scmp.8.32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: blt a1, a0, .LBB2_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: blt a2, a1, .LBB2_3
+; RV32I-NEXT: j .LBB2_4
+; RV32I-NEXT: .LBB2_2:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: bge a2, a1, .LBB2_4
+; RV32I-NEXT: .LBB2_3:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: .LBB2_4:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: scmp.8.32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sext.w a2, a0
+; RV64I-NEXT: sext.w a1, a1
+; RV64I-NEXT: blt a1, a2, .LBB2_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: blt a2, a1, .LBB2_3
+; RV64I-NEXT: j .LBB2_4
+; RV64I-NEXT: .LBB2_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bge a2, a1, .LBB2_4
+; RV64I-NEXT: .LBB2_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB2_4:
+; RV64I-NEXT: ret
+ %1 = call i8 @llvm.scmp(i32 %x, i32 %y)
+ ret i8 %1
+}
+
+define i8 @scmp.8.64(i64 %x, i64 %y) nounwind {
+; RV32I-LABEL: scmp.8.64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: beq a1, a3, .LBB3_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slt a4, a3, a1
+; RV32I-NEXT: bnez a4, .LBB3_3
+; RV32I-NEXT: j .LBB3_4
+; RV32I-NEXT: .LBB3_2:
+; RV32I-NEXT: sltu a4, a2, a0
+; RV32I-NEXT: beqz a4, .LBB3_4
+; RV32I-NEXT: .LBB3_3:
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: .LBB3_4:
+; RV32I-NEXT: beq a1, a3, .LBB3_6
+; RV32I-NEXT: # %bb.5:
+; RV32I-NEXT: slt a0, a1, a3
+; RV32I-NEXT: bnez a0, .LBB3_7
+; RV32I-NEXT: j .LBB3_8
+; RV32I-NEXT: .LBB3_6:
+; RV32I-NEXT: sltu a0, a0, a2
+; RV32I-NEXT: beqz a0, .LBB3_8
+; RV32I-NEXT: .LBB3_7:
+; RV32I-NEXT: li a4, -1
+; RV32I-NEXT: .LBB3_8:
+; RV32I-NEXT: mv a0, a4
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: scmp.8.64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: blt a1, a0, .LBB3_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: blt a2, a1, .LBB3_3
+; RV64I-NEXT: j .LBB3_4
+; RV64I-NEXT: .LBB3_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bge a2, a1, .LBB3_4
+; RV64I-NEXT: .LBB3_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB3_4:
+; RV64I-NEXT: ret
+ %1 = call i8 @llvm.scmp(i64 %x, i64 %y)
+ ret i8 %1
+}
+
+define i32 @scmp.32.32(i32 %x, i32 %y) nounwind {
+; RV32I-LABEL: scmp.32.32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: blt a1, a0, .LBB4_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: blt a2, a1, .LBB4_3
+; RV32I-NEXT: j .LBB4_4
+; RV32I-NEXT: .LBB4_2:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: bge a2, a1, .LBB4_4
+; RV32I-NEXT: .LBB4_3:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: .LBB4_4:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: scmp.32.32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sext.w a2, a0
+; RV64I-NEXT: sext.w a1, a1
+; RV64I-NEXT: blt a1, a2, .LBB4_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: blt a2, a1, .LBB4_3
+; RV64I-NEXT: j .LBB4_4
+; RV64I-NEXT: .LBB4_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bge a2, a1, .LBB4_4
+; RV64I-NEXT: .LBB4_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB4_4:
+; RV64I-NEXT: ret
+ %1 = call i32 @llvm.scmp(i32 %x, i32 %y)
+ ret i32 %1
+}
+
+define i32 @scmp.32.64(i64 %x, i64 %y) nounwind {
+; RV32I-LABEL: scmp.32.64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: beq a1, a3, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slt a4, a3, a1
+; RV32I-NEXT: bnez a4, .LBB5_3
+; RV32I-NEXT: j .LBB5_4
+; RV32I-NEXT: .LBB5_2:
+; RV32I-NEXT: sltu a4, a2, a0
+; RV32I-NEXT: beqz a4, .LBB5_4
+; RV32I-NEXT: .LBB5_3:
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: .LBB5_4:
+; RV32I-NEXT: beq a1, a3, .LBB5_6
+; RV32I-NEXT: # %bb.5:
+; RV32I-NEXT: slt a0, a1, a3
+; RV32I-NEXT: bnez a0, .LBB5_7
+; RV32I-NEXT: j .LBB5_8
+; RV32I-NEXT: .LBB5_6:
+; RV32I-NEXT: sltu a0, a0, a2
+; RV32I-NEXT: beqz a0, .LBB5_8
+; RV32I-NEXT: .LBB5_7:
+; RV32I-NEXT: li a4, -1
+; RV32I-NEXT: .LBB5_8:
+; RV32I-NEXT: mv a0, a4
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: scmp.32.64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: blt a1, a0, .LBB5_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: blt a2, a1, .LBB5_3
+; RV64I-NEXT: j .LBB5_4
+; RV64I-NEXT: .LBB5_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bge a2, a1, .LBB5_4
+; RV64I-NEXT: .LBB5_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB5_4:
+; RV64I-NEXT: ret
+ %1 = call i32 @llvm.scmp(i64 %x, i64 %y)
+ ret i32 %1
+}
+
+define i64 @scmp.64.64(i64 %x, i64 %y) nounwind {
+; RV32I-LABEL: scmp.64.64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a4, a0
+; RV32I-NEXT: beq a1, a3, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: slt a0, a3, a1
+; RV32I-NEXT: bnez a0, .LBB6_3
+; RV32I-NEXT: j .LBB6_4
+; RV32I-NEXT: .LBB6_2:
+; RV32I-NEXT: sltu a0, a2, a4
+; RV32I-NEXT: beqz a0, .LBB6_4
+; RV32I-NEXT: .LBB6_3:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: .LBB6_4:
+; RV32I-NEXT: beq a1, a3, .LBB6_6
+; RV32I-NEXT: # %bb.5:
+; RV32I-NEXT: slt a1, a1, a3
+; RV32I-NEXT: bnez a1, .LBB6_7
+; RV32I-NEXT: j .LBB6_8
+; RV32I-NEXT: .LBB6_6:
+; RV32I-NEXT: sltu a1, a4, a2
+; RV32I-NEXT: beqz a1, .LBB6_8
+; RV32I-NEXT: .LBB6_7:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: li a1, -1
+; RV32I-NEXT: .LBB6_8:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: scmp.64.64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: blt a1, a0, .LBB6_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: blt a2, a1, .LBB6_3
+; RV64I-NEXT: j .LBB6_4
+; RV64I-NEXT: .LBB6_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bge a2, a1, .LBB6_4
+; RV64I-NEXT: .LBB6_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB6_4:
+; RV64I-NEXT: ret
+ %1 = call i64 @llvm.scmp(i64 %x, i64 %y)
+ ret i64 %1
+}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll b/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll
new file mode 100644
index 00000000000000..e2a95eb974342d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/ucmp.ll
@@ -0,0 +1,370 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv32 -global-isel | FileCheck %s --check-prefix=RV32I
+; RUN: llc < %s -mtriple=riscv64 -global-isel | FileCheck %s --check-prefix=RV64I
+
+define i8 @ucmp.8.8(i8 zeroext %x, i8 zeroext %y) nounwind {
+; RV32I-LABEL: ucmp.8.8:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: bltu a1, a0, .LBB0_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: bltu a2, a1, .LBB0_3
+; RV32I-NEXT: j .LBB0_4
+; RV32I-NEXT: .LBB0_2:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: bgeu a2, a1, .LBB0_4
+; RV32I-NEXT: .LBB0_3:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: .LBB0_4:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ucmp.8.8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: bltu a1, a0, .LBB0_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: bltu a2, a1, .LBB0_3
+; RV64I-NEXT: j .LBB0_4
+; RV64I-NEXT: .LBB0_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bgeu a2, a1, .LBB0_4
+; RV64I-NEXT: .LBB0_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB0_4:
+; RV64I-NEXT: ret
+ %1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
+ ret i8 %1
+}
+
+define i8 @ucmp.8.16(i16 zeroext %x, i16 zeroext %y) nounwind {
+; RV32I-LABEL: ucmp.8.16:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: bltu a1, a0, .LBB1_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: bltu a2, a1, .LBB1_3
+; RV32I-NEXT: j .LBB1_4
+; RV32I-NEXT: .LBB1_2:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: bgeu a2, a1, .LBB1_4
+; RV32I-NEXT: .LBB1_3:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: .LBB1_4:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ucmp.8.16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: bltu a1, a0, .LBB1_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: bltu a2, a1, .LBB1_3
+; RV64I-NEXT: j .LBB1_4
+; RV64I-NEXT: .LBB1_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bgeu a2, a1, .LBB1_4
+; RV64I-NEXT: .LBB1_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB1_4:
+; RV64I-NEXT: ret
+ %1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
+ ret i8 %1
+}
+
+define i8 @ucmp.8.32(i32 %x, i32 %y) nounwind {
+; RV32I-LABEL: ucmp.8.32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: bltu a1, a0, .LBB2_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: bltu a2, a1, .LBB2_3
+; RV32I-NEXT: j .LBB2_4
+; RV32I-NEXT: .LBB2_2:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: bgeu a2, a1, .LBB2_4
+; RV32I-NEXT: .LBB2_3:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: .LBB2_4:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ucmp.8.32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: slli a2, a1, 32
+; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: srli a2, a2, 32
+; RV64I-NEXT: bltu a2, a1, .LBB2_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: bltu a1, a2, .LBB2_3
+; RV64I-NEXT: j .LBB2_4
+; RV64I-NEXT: .LBB2_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bgeu a1, a2, .LBB2_4
+; RV64I-NEXT: .LBB2_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB2_4:
+; RV64I-NEXT: ret
+ %1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
+ ret i8 %1
+}
+
+define i8 @ucmp.8.64(i64 %x, i64 %y) nounwind {
+; RV32I-LABEL: ucmp.8.64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: beq a1, a3, .LBB3_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sltu a4, a3, a1
+; RV32I-NEXT: bnez a4, .LBB3_3
+; RV32I-NEXT: j .LBB3_4
+; RV32I-NEXT: .LBB3_2:
+; RV32I-NEXT: sltu a4, a2, a0
+; RV32I-NEXT: beqz a4, .LBB3_4
+; RV32I-NEXT: .LBB3_3:
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: .LBB3_4:
+; RV32I-NEXT: beq a1, a3, .LBB3_6
+; RV32I-NEXT: # %bb.5:
+; RV32I-NEXT: sltu a0, a1, a3
+; RV32I-NEXT: bnez a0, .LBB3_7
+; RV32I-NEXT: j .LBB3_8
+; RV32I-NEXT: .LBB3_6:
+; RV32I-NEXT: sltu a0, a0, a2
+; RV32I-NEXT: beqz a0, .LBB3_8
+; RV32I-NEXT: .LBB3_7:
+; RV32I-NEXT: li a4, -1
+; RV32I-NEXT: .LBB3_8:
+; RV32I-NEXT: mv a0, a4
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ucmp.8.64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: bltu a1, a0, .LBB3_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: bltu a2, a1, .LBB3_3
+; RV64I-NEXT: j .LBB3_4
+; RV64I-NEXT: .LBB3_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bgeu a2, a1, .LBB3_4
+; RV64I-NEXT: .LBB3_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB3_4:
+; RV64I-NEXT: ret
+ %1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
+ ret i8 %1
+}
+
+define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind {
+; RV32I-LABEL: ucmp.32.32:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: bltu a1, a0, .LBB4_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: bltu a2, a1, .LBB4_3
+; RV32I-NEXT: j .LBB4_4
+; RV32I-NEXT: .LBB4_2:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: bgeu a2, a1, .LBB4_4
+; RV32I-NEXT: .LBB4_3:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: .LBB4_4:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ucmp.32.32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: slli a2, a1, 32
+; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: srli a2, a2, 32
+; RV64I-NEXT: bltu a2, a1, .LBB4_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: bltu a1, a2, .LBB4_3
+; RV64I-NEXT: j .LBB4_4
+; RV64I-NEXT: .LBB4_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bgeu a1, a2, .LBB4_4
+; RV64I-NEXT: .LBB4_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB4_4:
+; RV64I-NEXT: ret
+ %1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
+ ret i32 %1
+}
+
+define i32 @ucmp.32.32_sext(i32 signext %x, i32 signext %y) nounwind {
+; RV32I-LABEL: ucmp.32.32_sext:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: bltu a1, a0, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: bltu a2, a1, .LBB5_3
+; RV32I-NEXT: j .LBB5_4
+; RV32I-NEXT: .LBB5_2:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: bgeu a2, a1, .LBB5_4
+; RV32I-NEXT: .LBB5_3:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: .LBB5_4:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ucmp.32.32_sext:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: slli a2, a1, 32
+; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: srli a2, a2, 32
+; RV64I-NEXT: bltu a2, a1, .LBB5_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: bltu a1, a2, .LBB5_3
+; RV64I-NEXT: j .LBB5_4
+; RV64I-NEXT: .LBB5_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bgeu a1, a2, .LBB5_4
+; RV64I-NEXT: .LBB5_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB5_4:
+; RV64I-NEXT: ret
+ %1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
+ ret i32 %1
+}
+
+define i32 @ucmp.32.32_zext(i32 zeroext %x, i32 zeroext %y) nounwind {
+; RV32I-LABEL: ucmp.32.32_zext:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: bltu a1, a0, .LBB6_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: li a0, 0
+; RV32I-NEXT: bltu a2, a1, .LBB6_3
+; RV32I-NEXT: j .LBB6_4
+; RV32I-NEXT: .LBB6_2:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: bgeu a2, a1, .LBB6_4
+; RV32I-NEXT: .LBB6_3:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: .LBB6_4:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ucmp.32.32_zext:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: bltu a1, a0, .LBB6_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: bltu a2, a1, .LBB6_3
+; RV64I-NEXT: j .LBB6_4
+; RV64I-NEXT: .LBB6_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bgeu a2, a1, .LBB6_4
+; RV64I-NEXT: .LBB6_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB6_4:
+; RV64I-NEXT: ret
+ %1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
+ ret i32 %1
+}
+
+define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind {
+; RV32I-LABEL: ucmp.32.64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: beq a1, a3, .LBB7_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sltu a4, a3, a1
+; RV32I-NEXT: bnez a4, .LBB7_3
+; RV32I-NEXT: j .LBB7_4
+; RV32I-NEXT: .LBB7_2:
+; RV32I-NEXT: sltu a4, a2, a0
+; RV32I-NEXT: beqz a4, .LBB7_4
+; RV32I-NEXT: .LBB7_3:
+; RV32I-NEXT: li a4, 1
+; RV32I-NEXT: .LBB7_4:
+; RV32I-NEXT: beq a1, a3, .LBB7_6
+; RV32I-NEXT: # %bb.5:
+; RV32I-NEXT: sltu a0, a1, a3
+; RV32I-NEXT: bnez a0, .LBB7_7
+; RV32I-NEXT: j .LBB7_8
+; RV32I-NEXT: .LBB7_6:
+; RV32I-NEXT: sltu a0, a0, a2
+; RV32I-NEXT: beqz a0, .LBB7_8
+; RV32I-NEXT: .LBB7_7:
+; RV32I-NEXT: li a4, -1
+; RV32I-NEXT: .LBB7_8:
+; RV32I-NEXT: mv a0, a4
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ucmp.32.64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: bltu a1, a0, .LBB7_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: bltu a2, a1, .LBB7_3
+; RV64I-NEXT: j .LBB7_4
+; RV64I-NEXT: .LBB7_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bgeu a2, a1, .LBB7_4
+; RV64I-NEXT: .LBB7_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB7_4:
+; RV64I-NEXT: ret
+ %1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
+ ret i32 %1
+}
+
+define i64 @ucmp.64.64(i64 %x, i64 %y) nounwind {
+; RV32I-LABEL: ucmp.64.64:
+; RV32I: # %bb.0:
+; RV32I-NEXT: mv a4, a0
+; RV32I-NEXT: beq a1, a3, .LBB8_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: sltu a0, a3, a1
+; RV32I-NEXT: bnez a0, .LBB8_3
+; RV32I-NEXT: j .LBB8_4
+; RV32I-NEXT: .LBB8_2:
+; RV32I-NEXT: sltu a0, a2, a4
+; RV32I-NEXT: beqz a0, .LBB8_4
+; RV32I-NEXT: .LBB8_3:
+; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: .LBB8_4:
+; RV32I-NEXT: beq a1, a3, .LBB8_6
+; RV32I-NEXT: # %bb.5:
+; RV32I-NEXT: sltu a1, a1, a3
+; RV32I-NEXT: bnez a1, .LBB8_7
+; RV32I-NEXT: j .LBB8_8
+; RV32I-NEXT: .LBB8_6:
+; RV32I-NEXT: sltu a1, a4, a2
+; RV32I-NEXT: beqz a1, .LBB8_8
+; RV32I-NEXT: .LBB8_7:
+; RV32I-NEXT: li a0, -1
+; RV32I-NEXT: li a1, -1
+; RV32I-NEXT: .LBB8_8:
+; RV32I-NEXT: ret
+;
+; RV64I-LABEL: ucmp.64.64:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mv a2, a0
+; RV64I-NEXT: bltu a1, a0, .LBB8_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a0, 0
+; RV64I-NEXT: bltu a2, a1, .LBB8_3
+; RV64I-NEXT: j .LBB8_4
+; RV64I-NEXT: .LBB8_2:
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bgeu a2, a1, .LBB8_4
+; RV64I-NEXT: .LBB8_3:
+; RV64I-NEXT: li a0, -1
+; RV64I-NEXT: .LBB8_4:
+; RV64I-NEXT: ret
+ %1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
+ ret i64 %1
+}
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