[llvm] CodeGen: Eliminate dynamic relocations in the register superclass tables. (PR #119122)
Owen Anderson via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 8 01:59:55 PST 2024
https://github.com/resistor created https://github.com/llvm/llvm-project/pull/119122
None
>From a6579a72ce77ab124b2c5683706f28f15d9fe209 Mon Sep 17 00:00:00 2001
From: Owen Anderson <resistor at mac.com>
Date: Sun, 8 Dec 2024 22:57:55 +1300
Subject: [PATCH] CodeGen: Eliminate dynamic relocations in the register
superclass tables.
---
llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 4 ++--
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 14 +++++++-------
llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp | 5 +++--
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 14 +++++++-------
llvm/lib/Target/X86/X86RegisterInfo.cpp | 3 ++-
llvm/utils/TableGen/RegisterInfoEmitter.cpp | 10 +++++-----
6 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 292fa3c94969be..9181fef39e7b04 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -46,7 +46,7 @@ class TargetRegisterClass {
public:
using iterator = const MCPhysReg *;
using const_iterator = const MCPhysReg *;
- using sc_iterator = const TargetRegisterClass* const *;
+ using sc_iterator = const unsigned *;
// Instance variables filled by tablegen, do not use!
const MCRegisterClass *MC;
@@ -185,7 +185,7 @@ class TargetRegisterClass {
/// Return true if this TargetRegisterClass is a subset
/// class of at least one other TargetRegisterClass.
bool isASubClass() const {
- return SuperClasses[0] != nullptr;
+ return SuperClasses[0] != ~0U;
}
/// Returns the preferred order for allocating registers from this register
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index a1f068f0e049bd..2df4ee3b84bc19 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -262,30 +262,30 @@ bool ARMBaseRegisterInfo::isInlineAsmReadOnlyReg(const MachineFunction &MF,
const TargetRegisterClass *
ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const {
- const TargetRegisterClass *Super = RC;
+ unsigned SuperID = RC->getID();
TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
do {
- switch (Super->getID()) {
+ switch (SuperID) {
case ARM::GPRRegClassID:
case ARM::SPRRegClassID:
case ARM::DPRRegClassID:
case ARM::GPRPairRegClassID:
- return Super;
+ return getRegClass(SuperID);
case ARM::QPRRegClassID:
case ARM::QQPRRegClassID:
case ARM::QQQQPRRegClassID:
if (MF.getSubtarget<ARMSubtarget>().hasNEON())
- return Super;
+ return getRegClass(SuperID);
break;
case ARM::MQPRRegClassID:
case ARM::MQQPRRegClassID:
case ARM::MQQQQPRRegClassID:
if (MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps())
- return Super;
+ return getRegClass(SuperID);
break;
}
- Super = *I++;
- } while (Super);
+ SuperID = *I++;
+ } while (SuperID != ~0U);
return RC;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index d4d121e4380089..31840d9757f7e8 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -431,8 +431,9 @@ unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
return WSub[GenIdx];
}
- if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
- return getHexagonSubRegIndex(*SuperRC, GenIdx);
+ unsigned SuperID = *RC.getSuperClasses();
+ if (SuperID != ~0U)
+ return getHexagonSubRegIndex(*getRegClass(SuperID), GenIdx);
llvm_unreachable("Invalid register class");
}
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 43dfc4108f8384..5feda6bd18cee3 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -692,21 +692,21 @@ PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
InflateGPRC++;
}
- for (const auto *I = RC->getSuperClasses(); *I; ++I) {
- if (getRegSizeInBits(**I) != getRegSizeInBits(*RC))
+ for (const unsigned *I = RC->getSuperClasses(); *I != ~0U; ++I) {
+ if (getRegSizeInBits(*getRegClass(*I)) != getRegSizeInBits(*RC))
continue;
- switch ((*I)->getID()) {
+ switch (*I) {
case PPC::VSSRCRegClassID:
- return Subtarget.hasP8Vector() ? *I : DefaultSuperclass;
+ return Subtarget.hasP8Vector() ? getRegClass(*I) : DefaultSuperclass;
case PPC::VSFRCRegClassID:
case PPC::VSRCRegClassID:
- return *I;
+ return getRegClass(*I);
case PPC::VSRpRCRegClassID:
- return Subtarget.pairedVectorMemops() ? *I : DefaultSuperclass;
+ return Subtarget.pairedVectorMemops() ? getRegClass(*I) : DefaultSuperclass;
case PPC::ACCRCRegClassID:
case PPC::UACCRCRegClassID:
- return Subtarget.hasMMA() ? *I : DefaultSuperclass;
+ return Subtarget.hasMMA() ? getRegClass(*I) : DefaultSuperclass;
}
}
}
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
index 50db211c99d882..96c42c559304cc 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -172,7 +172,8 @@ X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
if (getRegSizeInBits(*Super) == getRegSizeInBits(*RC))
return Super;
}
- Super = *I++;
+ Super = (*I != ~0U) ? getRegClass(*I) : nullptr;
+ ++I;
} while (Super);
return RC;
}
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index a6f87119aca5ba..5be1a6c9a45c69 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1286,8 +1286,8 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) {
}
OS << "};\n";
- OS << "\nstatic const TargetRegisterClass *const "
- << "NullRegClasses[] = { nullptr };\n\n";
+ OS << "\nstatic const unsigned "
+ << "NullRegClasses[] = { ~0U };\n\n";
// Emit register class bit mask tables. The first bit mask emitted for a
// register class, RC, is the set of sub-classes, including RC itself.
@@ -1348,11 +1348,11 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) {
if (Supers.empty())
continue;
- OS << "static const TargetRegisterClass *const " << RC.getName()
+ OS << "static unsigned const " << RC.getName()
<< "Superclasses[] = {\n";
for (const auto *Super : Supers)
- OS << " &" << Super->getQualifiedName() << "RegClass,\n";
- OS << " nullptr\n};\n\n";
+ OS << " " << Super->getQualifiedIdName() << ",\n";
+ OS << " ~0U\n};\n\n";
}
// Emit methods.
More information about the llvm-commits
mailing list