[llvm] [X86][Codegen] Shuffle certain shifts on i8 vectors to create opportunity for vectorized shift instructions (PR #117980)

[Simon Pilgrim via llvm-commits]

RKSimon wrote:

Lowering occurs in the DAG which handles each basic block independently without any real understanding of whether its part of a hot loop etc. - a compile flag would struggle to account for every case. This issue has come up a few times recently but I'm not sure how easy it'd be to delay things like this to a MachineLICM pass afterwards given how different the codegen could turn out to be.

Depending on your target CPU I did start work on generic vXi8 shift lowering using GFNI instructions: https://github.com/llvm/llvm-project/pull/89644 which I haven't had time to go back to, have you looked at anything similar?

https://github.com/llvm/llvm-project/pull/117980