[llvm] 52646d0 - [GISel] Teach computeKnownBitsImpl to handle COPY instructions that change bit width. (#118924)

[via llvm-commits]

Author: Craig Topper
Date: 2024-12-06T21:31:19-08:00
New Revision: 52646d087cdecd217436b2714f94b84c46b5720a

URL: https://github.com/llvm/llvm-project/commit/52646d087cdecd217436b2714f94b84c46b5720a
DIFF: https://github.com/llvm/llvm-project/commit/52646d087cdecd217436b2714f94b84c46b5720a.diff

LOG: [GISel] Teach computeKnownBitsImpl to handle COPY instructions that change bit width. (#118924)

The sexti32 ComplexRenderFn on RISCV calls computeNumSignBits which
calls computeKnownBits.

I encountered a case where we looked through a G_PHI and found a COPY
that was created from an already selected G_TRUNC from s64 to s32. s32
and s64 integers on RISC-V end up in the same register class. s32 G_PHI
is legal to allow f32 phis on RV64. The COPY inherited the types from the
original G_TRUNC so the source and destination virtual registers have
different widths.

This patch uses KnownBits::anyextOrTrunc to adjust the width when they
mismatch.

Added: 
    llvm/test/CodeGen/RISCV/GlobalISel/knownbits-copy-crash.mir

Modified: 
    llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
index 30cd3ce3baa502..6c15ed3423d3bd 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp
@@ -253,6 +253,7 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
         // For COPYs we don't do anything, don't increase the depth.
         computeKnownBitsImpl(SrcReg, Known2, DemandedElts,
                              Depth + (Opcode != TargetOpcode::COPY));
+        Known2 = Known2.anyextOrTrunc(BitWidth);
         Known = Known.intersectWith(Known2);
         // If we reach a point where we don't know anything
         // just stop looking through the operands.

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/knownbits-copy-crash.mir b/llvm/test/CodeGen/RISCV/GlobalISel/knownbits-copy-crash.mir
new file mode 100644
index 00000000000000..99be88b55ea817
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/knownbits-copy-crash.mir
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -mattr=+zbb,+f -run-pass=instruction-select %s -o - | FileCheck %s
+
+---
+name:            foo
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr = PHI [[COPY]], %bb.0, %6, %bb.1
+  ; CHECK-NEXT:   [[ADDIW:%[0-9]+]]:gpr = ADDIW [[PHI]], 0
+  ; CHECK-NEXT:   [[FCVT_S_W:%[0-9]+]]:fpr32 = nofpexcept FCVT_S_W [[ADDIW]], 7
+  ; CHECK-NEXT:   [[FCVT_W_S:%[0-9]+]]:gpr = nofpexcept FCVT_W_S [[FCVT_S_W]], 1
+  ; CHECK-NEXT:   PseudoBR %bb.1
+  bb.1:
+    %7:gprb(s64) = G_CONSTANT i64 0
+    %3:gprb(s32) = G_TRUNC %7(s64)
+
+  bb.2:
+    %0:gprb(s32) = G_PHI %3(s32), %bb.1, %2(s32), %bb.2
+    %6:gprb(s64) = G_SEXT %0(s32)
+    %1:fprb(s32) = G_SITOFP %6(s64)
+    %5:gprb(s64) = G_FCVT_W_RV64 %1(s32), 1
+    %2:gprb(s32) = G_TRUNC %5(s64)
+    G_BR %bb.2
+
+...