[llvm] [AMDGPU][Scheduler] Refactor VGPR rematerialization during scheduling (PR #118722)

[Matt Arsenault via llvm-commits]

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@@ -1716,6 +1712,11 @@ bool PreRARematStage::isTriviallyReMaterializable(const MachineInstr &MI) {
   if (!DAG.TII->isTriviallyReMaterializable(MI))
     return false;
 
+  // Even though TargetInstrInfo::isReallyTriviallyReMaterializable already
+  // ensures that the instruction has no virtual register uses,
+  // SIInstrInfo::isReallyTriviallyReMaterializable may consider an instruction
+  // rematerializable and return before calling its parent's method, so we need
+  // to double-check here.
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arsenm wrote:

> Our SIInstrInfo override considers that rematerializing VOP{1,2,3} instructions with virtual register uses is trivial, which I don't really agree with

I think this is one of those cases that was supposed to be moved up to the generic implementation. The actual uses consider liveness, so it shouldn't be baked into the low level check

https://github.com/llvm/llvm-project/pull/118722