[llvm] [AMDGPU] In instruction selector, allow copy from physical reg to s1 (PR #96157)

[Matt Arsenault via llvm-commits]

================
@@ -0,0 +1,138 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
+
+---
+name: copy_sgpr_to_s1_vcc
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; WAVE32-LABEL: name: copy_sgpr_to_s1_vcc
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32-NEXT: {{  $}}
+    ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY $sgpr0
+    ; WAVE32-NEXT: [[VMOV1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    ; WAVE32-NEXT: [[VMOV2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32-NEXT: [[VCND:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[VMOV2]], 0, [[VMOV1]], [[COPY]], implicit $exec
+    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[VCND]]
+    ;
+    %0:vcc(s1) = COPY $sgpr0
+    %2:vgpr(s32) = G_CONSTANT i32 1
+    %3:vgpr(s32) = G_CONSTANT i32 0
+    %1:vgpr(s32) = G_SELECT %0:vcc(s1), %2:vgpr, %3:vgpr
+    S_ENDPGM 0, implicit %1:vgpr(s32)
+...
+
+---
+name: copy_sgpr_to_s1_sreg_32_xm0_xexec
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; WAVE32-LABEL: name: copy_sgpr_to_s1_sreg_32_xm0_xexec
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32-NEXT: {{  $}}
+    ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY $sgpr0
+    ; WAVE32-NEXT: [[VMOV1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    ; WAVE32-NEXT: [[VMOV2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32-NEXT: [[VCND:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[VMOV2]], 0, [[VMOV1]], [[COPY]], implicit $exec
+    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[VCND]]
+    ;
+    %0:sreg_32_xm0_xexec(s1) = COPY $sgpr0
+    %2:vgpr(s32) = G_CONSTANT i32 1
+    %3:vgpr(s32) = G_CONSTANT i32 0
+    %1:vgpr(s32) = G_SELECT %0:sreg_32_xm0_xexec(s1), %2:vgpr, %3:vgpr
+    S_ENDPGM 0, implicit %1:vgpr(s32)
+...
+
+---
+name: copy_sgpr_to_s1_vgpr
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; WAVE32-LABEL: name: copy_sgpr_to_s1_vgpr
+    ; WAVE32: liveins: $sgpr0
+    ; WAVE32-NEXT: {{  $}}
+    ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $sgpr0
+    ; WAVE32-NEXT: [[VMOV1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    ; WAVE32-NEXT: [[VMOV2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY]]
+    ; WAVE32-NEXT: [[VCND:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[VMOV2]], 0, [[VMOV1]], [[COPY2]], implicit $exec
+    ; WAVE32-NEXT: S_ENDPGM 0, implicit [[VCND]]
+    ;
+    %0:vgpr(s1) = COPY $sgpr0
+    %2:vgpr(s32) = G_CONSTANT i32 1
+    %3:vgpr(s32) = G_CONSTANT i32 0
+    %1:vgpr(s32) = G_SELECT %0:vgpr(s1), %2:vgpr, %3:vgpr
+    S_ENDPGM 0, implicit %1:vgpr(s32)
+...
+
+---
+name: copy_scc_to_s1_vcc
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    ; WAVE32-LABEL: name: copy_scc_to_s1_vcc
+    ; WAVE32:      [[COPY:%[0-9]+]]:sreg_32_xm0_xexec = COPY $scc
+    ; WAVE32-NEXT: [[VMOV1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    ; WAVE32-NEXT: [[VMOV2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; WAVE32-NEXT: [[VCND:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[VMOV2]], 0, [[VMOV1]], [[COPY]], implicit $exec
----------------
arsenm wrote:

This case still looks wrong, but we don't actually want this to ever be produced. 

https://github.com/llvm/llvm-project/pull/96157