[llvm] [SelectionDAG] Add an ISD node for vector.extract.last.active (PR #118810)

[Graham Hunter via llvm-commits]

huntergr-arm wrote:

I've changed the base method of lowering for the vector.extract.last.active to use a dedicated ISD node, then implemented expansion in LegalizeVectorOps. I ran into a few problems along the way regarding legalization of types and operations being added that weren't recursively expanded if required by the target, leading to selection failures. I've put in workarounds for now, but we'll want something better before this PR lands.

One of the problems is the result of calling `TLI.getBitWidthForCttzElements(...)`. For AArch64, we sometimes end up with a VT that's a little too small for a vector, giving us an illegal type of `v4i8` when trying to extract from a `v4i32`. RISC-V on the other hand seems to always use i64, giving us the illegal `nxv16i64` when extracting from `nxv16i8`, which resulted in trying to expand vecreduce_umax for a scalable vector.

The AArch64 backend can probably avoid the problem by being a bit more strict about which operations are marked as Expand vs. Legal. Not sure what those working on RVV would like to do here.

https://github.com/llvm/llvm-project/pull/112738 will be updated once this work is complete.

Currently the changes result in worse codegen for both AArch64 and RISC-V targets, but implementing custom lowering will be easy with just the single node to match. I do wonder if there's a better representation, however. A couple of options come to mind:

1. Split into an `extract_last_active` node without a passthru, and use a separate or reduction + scalar select sequence if the passthru from IR wasn't poison.
2. Split into a `find_last_active_index` which only finds the index of the last active lane, then use the existing `extract_vector_elt` node (and the or reduction + select if needed, as with the first option).

I won't be able to continue this before next year, so no hurry on review.

https://github.com/llvm/llvm-project/pull/118810