[llvm] [AMDGPU] Handle hazard in v_scalef32_sr_fp4_* conversions (PR #118589)

[Matt Arsenault via llvm-commits]

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@@ -657,9 +664,16 @@ bool isTrue16Inst(unsigned Opc) {
   return Info ? Info->IsTrue16 : false;
 }
 
-bool isFP8DstSelInst(unsigned Opc) {
-  const FP8DstByteSelInfo *Info = getFP8DstByteSelHelper(Opc);
-  return Info ? Info->HasFP8DstByteSel : false;
+FPType getFPDstSelType(unsigned Opc) {
+  const FP8DstByteSelInfo *Info8 = getFP8DstByteSelHelper(Opc);
+  if (Info8 && Info8->HasFP8DstByteSel)
+    return FPType::FP8;
+
+  const FP4DstByteSelInfo *Info4 = getFP4DstByteSelHelper(Opc);
+  if (Info4 && Info4->HasFP4DstByteSel)
+    return FPType::FP4;
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arsenm wrote:

Yes, I'm saying to generate one searchable table with the enum as one of the fields. See MFMA_F8F6F4_Info or MAIInstInfo for an example

https://github.com/llvm/llvm-project/pull/118589