[llvm] [GlobalISel] Combine into abd[su] and legalize abd[su] (PR #118865)

[Matt Arsenault via llvm-commits]

Thorsten =?utf-8?q?Schütt?= <schuett at gmail.com>,
Thorsten =?utf-8?q?Schütt?= <schuett at gmail.com>,
Thorsten =?utf-8?q?Schütt?= <schuett at gmail.com>,
Thorsten =?utf-8?q?Schütt?= <schuett at gmail.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/118865 at github.com>


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@@ -7865,3 +7865,49 @@ bool CombinerHelper::matchSuboCarryOut(const MachineInstr &MI,
 
   return false;
 }
+
+// sub(smax(lhs,rhs), smin(lhs,rhs)) -> abds(lhs, rhs)
+bool CombinerHelper::matchSubAbds(const MachineInstr &MI,
+                                  BuildFnTy &MatchInfo) {
+  const GSub *Sub = cast<GSub>(&MI);
+  const GMMaxMinOp *LHS = cast<GMMaxMinOp>(MRI.getVRegDef(Sub->getLHSReg()));
+  const GMMaxMinOp *RHS = cast<GMMaxMinOp>(MRI.getVRegDef(Sub->getLHSReg()));
+
+  if (!MRI.hasOneNonDBGUse(LHS->getReg(0)) ||
+      !MRI.hasOneNonDBGUse(RHS->getReg(0)))
+    return false;
+
+  Register Dst = Sub->getReg(0);
+  LLT DstTy = MRI.getType(Dst);
+
+  if (!isLegalOrBeforeLegalizer({TargetOpcode::G_ABDS, {DstTy}}))
+    return false;
+
+  MatchInfo = [=](MachineIRBuilder &B) {
+    B.buildAbds(Dst, LHS->getLHSReg(), LHS->getRHSReg());
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arsenm wrote:

Can do this apply in pure tablegen?

https://github.com/llvm/llvm-project/pull/118865