[llvm] [AMDGPU] New aliases v_add3_nc_u32 and v_xor_add_u32 (PR #118970)

[Jay Foad via llvm-commits]

https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/118970

This is for compatibility with SP3.


>From 384356844ec652ec6a95561a2656f089f5599b3e Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Fri, 6 Dec 2024 13:29:33 +0000
Subject: [PATCH] [AMDGPU] New aliases v_add3_nc_u32 and v_xor_add_u32

This is for compatibility with SP3.
---
 llvm/lib/Target/AMDGPU/VOP3Instructions.td   | 5 +++++
 llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s   | 6 ++++++
 llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s | 6 ++++++
 3 files changed, 17 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 47b60bb0fdab30..01c23866b9d485 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -1750,6 +1750,11 @@ defm V_OR_B16_fake16       : VOP3Only_Realtriple_t16_gfx11_gfx12<0x363, "v_or_b1
 defm V_XOR_B16_t16         : VOP3Only_Realtriple_t16_gfx11_gfx12<0x364, "v_xor_b16">;
 defm V_XOR_B16_fake16      : VOP3Only_Realtriple_t16_gfx11_gfx12<0x364, "v_xor_b16">;
 
+let AssemblerPredicate = isGFX11Plus in {
+  def : AMDGPUMnemonicAlias<"v_add3_nc_u32", "v_add3_u32">;
+  def : AMDGPUMnemonicAlias<"v_xor_add_u32", "v_xad_u32">;
+}
+
 //===----------------------------------------------------------------------===//
 // GFX10.
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s
index ad1d652a2ac1df..9803b1b050d8a3 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_alias.s
@@ -6,3 +6,9 @@ v_cvt_pknorm_i16_f16 v5, v1, v2
 
 v_cvt_pknorm_u16_f16 v5, v1, v2
 // GFX11: v_cvt_pk_norm_u16_f16 v5, v1, v2        ; encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_add3_nc_u32 v5, v1, v2, s3
+// GFX11: v_add3_u32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00]
+
+v_xor_add_u32 v5, v1, v2, s3
+// GFX11: v_xad_u32 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x45,0xd6,0x01,0x05,0x0e,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
index 7a1ebbd9e19a8a..f5d5bd580cef83 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_aliases.s
@@ -47,3 +47,9 @@ v_cvt_pknorm_i16_f16 v5, v1, v2
 
 v_cvt_pknorm_u16_f16 v5, v1, v2
 // GFX12: v_cvt_pk_norm_u16_f16 v5, v1, v2        ; encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_add3_nc_u32 v5, v1, v2, s3
+// GFX12: v_add3_u32 v5, v1, v2, s3               ; encoding: [0x05,0x00,0x55,0xd6,0x01,0x05,0x0e,0x00]
+
+v_xor_add_u32 v5, v1, v2, s3
+// GFX12: v_xad_u32 v5, v1, v2, s3                ; encoding: [0x05,0x00,0x45,0xd6,0x01,0x05,0x0e,0x00]