[llvm] [RegAlloc] Scale the spill weight by the weight of register class (PR #113675)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> @JonPsson1 the cond-move-regalloc-hints.mir change here looks like a regression. Can you have a look why this happens?

Thanks for taking a look!
I have some impressions about this test `cond-move-regalloc-hints.mir` when fixing these tests that are not using `utils/update_llc_test_checks.py`. :-)
I don't know much about SystemZ, but it seems to be an improvment?
![图片](https://github.com/user-attachments/assets/8bd2f53c-06fd-4d24-a13a-74355f7a2d93)


https://github.com/llvm/llvm-project/pull/113675