[llvm] [TRI][RISCV] Add methods to get common register class of two registers (PR #118435)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 5 23:00:40 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/118435
>From 7aee1b76489b87dabadf5123f2089c66465e8601 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Tue, 3 Dec 2024 14:50:18 +0800
Subject: [PATCH 1/3] [TRI][RISCV] Add methods to get common register class of
two registers
Here we add two methods `getCommonMinimalPhysRegClass` and a LLT
version `getCommonMinimalPhysRegClassLLT`, which return the most
sub register class of the right type that contains these two input
registers.
We don't overload the `getMinimalPhysRegClass` as there will be
ambiguities.
We use it to simplify some code in RISC-V target.
---
.../include/llvm/CodeGen/TargetRegisterInfo.h | 15 ++++++++
llvm/lib/CodeGen/TargetRegisterInfo.cpp | 37 +++++++++++++++++++
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 16 +++-----
3 files changed, 57 insertions(+), 11 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 292fa3c94969be..d9dfbbc5d66219 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -350,6 +350,13 @@ class TargetRegisterInfo : public MCRegisterInfo {
const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg,
MVT VT = MVT::Other) const;
+ /// Returns the common Register Class of two physical registers of the given
+ /// type, picking the most sub register class of the right type that contains
+ /// these two physregs.
+ const TargetRegisterClass *
+ getCommonMinimalPhysRegClass(MCRegister Reg1, MCRegister Reg2,
+ MVT VT = MVT::Other) const;
+
/// Returns the Register Class of a physical register of the given type,
/// picking the most sub register class of the right type that contains this
/// physreg. If there is no register class compatible with the given type,
@@ -357,6 +364,14 @@ class TargetRegisterInfo : public MCRegisterInfo {
const TargetRegisterClass *getMinimalPhysRegClassLLT(MCRegister Reg,
LLT Ty = LLT()) const;
+ /// Returns the common Register Class of two physical registers of the given
+ /// type, picking the most sub register class of the right type that contains
+ /// these two physregs. If there is no register class compatible with the
+ /// given type, returns nullptr.
+ const TargetRegisterClass *
+ getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2,
+ LLT Ty = LLT()) const;
+
/// Return the maximal subclass of the given register class that is
/// allocatable or NULL.
const TargetRegisterClass *
diff --git a/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
index 032f1a33e75c43..4eff8bdbf744be 100644
--- a/llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -222,6 +222,25 @@ TargetRegisterInfo::getMinimalPhysRegClass(MCRegister reg, MVT VT) const {
return BestRC;
}
+const TargetRegisterClass *TargetRegisterInfo::getCommonMinimalPhysRegClass(
+ MCRegister Reg1, MCRegister Reg2, MVT VT) const {
+ assert(Register::isPhysicalRegister(Reg1) &&
+ Register::isPhysicalRegister(Reg2) &&
+ "Reg1/Reg2 must be a physical register");
+
+ // Pick the most sub register class of the right type that contains
+ // this physreg.
+ const TargetRegisterClass *BestRC = nullptr;
+ for (const TargetRegisterClass *RC : regclasses()) {
+ if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
+ RC->contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC)))
+ BestRC = RC;
+ }
+
+ assert(BestRC && "Couldn't find the register class");
+ return BestRC;
+}
+
const TargetRegisterClass *
TargetRegisterInfo::getMinimalPhysRegClassLLT(MCRegister reg, LLT Ty) const {
assert(Register::isPhysicalRegister(reg) &&
@@ -239,6 +258,24 @@ TargetRegisterInfo::getMinimalPhysRegClassLLT(MCRegister reg, LLT Ty) const {
return BestRC;
}
+const TargetRegisterClass *TargetRegisterInfo::getCommonMinimalPhysRegClassLLT(
+ MCRegister Reg1, MCRegister Reg2, LLT Ty) const {
+ assert(Register::isPhysicalRegister(Reg1) &&
+ Register::isPhysicalRegister(Reg2) &&
+ "Reg1/Reg2 must be a physical register");
+
+ // Pick the most sub register class of the right type that contains
+ // this physreg.
+ const TargetRegisterClass *BestRC = nullptr;
+ for (const TargetRegisterClass *RC : regclasses()) {
+ if ((!Ty.isValid() || isTypeLegalForClass(*RC, Ty)) &&
+ RC->contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC)))
+ BestRC = RC;
+ }
+
+ return BestRC;
+}
+
/// getAllocatableSetForRC - Toggle the bits that represent allocatable
/// registers for the specific register class.
static void getAllocatableSetForRC(const MachineFunction &MF,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 47273d6bc06d65..017a1c514879b4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -562,17 +562,11 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
// VR->VR copies.
- static const TargetRegisterClass *RVVRegClasses[] = {
- &RISCV::VRRegClass, &RISCV::VRM2RegClass, &RISCV::VRM4RegClass,
- &RISCV::VRM8RegClass, &RISCV::VRN2M1RegClass, &RISCV::VRN2M2RegClass,
- &RISCV::VRN2M4RegClass, &RISCV::VRN3M1RegClass, &RISCV::VRN3M2RegClass,
- &RISCV::VRN4M1RegClass, &RISCV::VRN4M2RegClass, &RISCV::VRN5M1RegClass,
- &RISCV::VRN6M1RegClass, &RISCV::VRN7M1RegClass, &RISCV::VRN8M1RegClass};
- for (const auto &RegClass : RVVRegClasses) {
- if (RegClass->contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RegClass);
- return;
- }
+ const TargetRegisterClass *RegClass =
+ TRI->getCommonMinimalPhysRegClass(SrcReg, DstReg);
+ if (RISCVRegisterInfo::isRVVRegClass(RegClass)) {
+ copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RegClass);
+ return;
}
llvm_unreachable("Impossible reg-to-reg copy");
>From 7e898ca3088bc906de5a991429eb265d30ecf91d Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 5 Dec 2024 20:52:40 +0800
Subject: [PATCH 2/3] Use hasSuperClassEq in FindRegWithEncoding
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 017a1c514879b4..10b758a2b133af 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -390,7 +390,7 @@ void RISCVInstrInfo::copyPhysRegVector(
auto FindRegWithEncoding = [TRI](const TargetRegisterClass &RegClass,
uint16_t Encoding) {
MCRegister Reg = RISCV::V0 + Encoding;
- if (&RegClass == &RISCV::VRRegClass)
+ if (RegClass.hasSuperClassEq(&RISCV::VRRegClass))
return Reg;
return TRI->getMatchingSuperReg(Reg, RISCV::sub_vrm1_0, &RegClass);
};
>From ba1d49ad188a74842926574c544a19f3e059e3d7 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Fri, 6 Dec 2024 14:59:53 +0800
Subject: [PATCH 3/3] Get LMUL from TSFlags
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 10b758a2b133af..116dea2dba63c1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -390,7 +390,7 @@ void RISCVInstrInfo::copyPhysRegVector(
auto FindRegWithEncoding = [TRI](const TargetRegisterClass &RegClass,
uint16_t Encoding) {
MCRegister Reg = RISCV::V0 + Encoding;
- if (RegClass.hasSuperClassEq(&RISCV::VRRegClass))
+ if (RISCVRI::getLMul(RegClass.TSFlags) == RISCVII::LMUL_1)
return Reg;
return TRI->getMatchingSuperReg(Reg, RISCV::sub_vrm1_0, &RegClass);
};
More information about the llvm-commits
mailing list