[llvm] 37b10af - [RISCV][GISel] Use correct shift width for GIShiftMask32 ComplexOperandMatcher.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 5 16:00:30 PST 2024
Author: Craig Topper
Date: 2024-12-05T15:52:41-08:00
New Revision: 37b10af6a0c0f39ac102dda4490f447122b550ef
URL: https://github.com/llvm/llvm-project/commit/37b10af6a0c0f39ac102dda4490f447122b550ef
DIFF: https://github.com/llvm/llvm-project/commit/37b10af6a0c0f39ac102dda4490f447122b550ef.diff
LOG: [RISCV][GISel] Use correct shift width for GIShiftMask32 ComplexOperandMatcher.
We should use 32 instead of XLen. This allows us to remove
'and X, 31' from the shift amount.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/RISCVGISel.td
llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 6ddc447da1a563..d525834ce76c2c 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -83,7 +83,14 @@ class RISCVInstructionSelector : public InstructionSelector {
bool selectMergeValues(MachineInstr &MI, MachineIRBuilder &MIB) const;
bool selectUnmergeValues(MachineInstr &MI, MachineIRBuilder &MIB) const;
- ComplexRendererFns selectShiftMask(MachineOperand &Root) const;
+ ComplexRendererFns selectShiftMask(MachineOperand &Root,
+ unsigned ShiftWidth) const;
+ ComplexRendererFns selectShiftMaskXLen(MachineOperand &Root) const {
+ return selectShiftMask(Root, STI.getXLen());
+ }
+ ComplexRendererFns selectShiftMask32(MachineOperand &Root) const {
+ return selectShiftMask(Root, 32);
+ }
ComplexRendererFns selectAddrRegImm(MachineOperand &Root) const;
ComplexRendererFns selectSExtBits(MachineOperand &Root, unsigned Bits) const;
@@ -172,22 +179,18 @@ RISCVInstructionSelector::RISCVInstructionSelector(
}
InstructionSelector::ComplexRendererFns
-RISCVInstructionSelector::selectShiftMask(MachineOperand &Root) const {
+RISCVInstructionSelector::selectShiftMask(MachineOperand &Root,
+ unsigned ShiftWidth) const {
if (!Root.isReg())
return std::nullopt;
using namespace llvm::MIPatternMatch;
- Register RootReg = Root.getReg();
- Register ShAmtReg = RootReg;
- const LLT ShiftLLT = MRI->getType(RootReg);
- unsigned ShiftWidth = ShiftLLT.getSizeInBits();
- assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!");
+ Register ShAmtReg = Root.getReg();
// Peek through zext.
Register ZExtSrcReg;
- if (mi_match(ShAmtReg, *MRI, m_GZExt(m_Reg(ZExtSrcReg)))) {
+ if (mi_match(ShAmtReg, *MRI, m_GZExt(m_Reg(ZExtSrcReg))))
ShAmtReg = ZExtSrcReg;
- }
APInt AndMask;
Register AndSrcReg;
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 9670e4b07068a2..361d3f3c7494cd 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -76,10 +76,10 @@ def gi_trailing_zero : GICustomOperandRenderer<"renderTrailingZeros">,
// should add a LowLevelTypeByHwMode, and use that to define our XLenLLT instead
// here.
def GIShiftMaskXLen :
- GIComplexOperandMatcher<s32, "selectShiftMask">,
+ GIComplexOperandMatcher<s32, "selectShiftMaskXLen">,
GIComplexPatternEquiv<shiftMaskXLen>;
def GIShiftMask32 :
- GIComplexOperandMatcher<s32, "selectShiftMask">,
+ GIComplexOperandMatcher<s64, "selectShiftMask32">,
GIComplexPatternEquiv<shiftMask32>;
def gi_sh1add_op : GIComplexOperandMatcher<s32, "selectSHXADDOp<1>">,
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
index 5beebe5bbcd973..51a84f5e93e31c 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll
@@ -108,9 +108,7 @@ define signext i32 @rol_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: rol_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: neg a2, a1
-; RV64I-NEXT: andi a1, a1, 31
; RV64I-NEXT: sllw a1, a0, a1
-; RV64I-NEXT: andi a2, a2, 31
; RV64I-NEXT: srlw a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
@@ -128,9 +126,7 @@ define void @rol_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind {
; RV64I-LABEL: rol_i32_nosext:
; RV64I: # %bb.0:
; RV64I-NEXT: neg a3, a1
-; RV64I-NEXT: andi a1, a1, 31
; RV64I-NEXT: sllw a1, a0, a1
-; RV64I-NEXT: andi a3, a3, 31
; RV64I-NEXT: srlw a0, a0, a3
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: sw a0, 0(a2)
@@ -151,9 +147,7 @@ define signext i32 @rol_i32_neg_constant_rhs(i32 signext %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -2
; RV64I-NEXT: neg a2, a0
-; RV64I-NEXT: andi a0, a0, 31
; RV64I-NEXT: sllw a0, a1, a0
-; RV64I-NEXT: andi a2, a2, 31
; RV64I-NEXT: srlw a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
@@ -192,9 +186,7 @@ define signext i32 @ror_i32(i32 signext %a, i32 signext %b) nounwind {
; RV64I-LABEL: ror_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: neg a2, a1
-; RV64I-NEXT: andi a1, a1, 31
; RV64I-NEXT: srlw a1, a0, a1
-; RV64I-NEXT: andi a2, a2, 31
; RV64I-NEXT: sllw a0, a0, a2
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: ret
@@ -212,9 +204,7 @@ define void @ror_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind {
; RV64I-LABEL: ror_i32_nosext:
; RV64I: # %bb.0:
; RV64I-NEXT: neg a3, a1
-; RV64I-NEXT: andi a1, a1, 31
; RV64I-NEXT: srlw a1, a0, a1
-; RV64I-NEXT: andi a3, a3, 31
; RV64I-NEXT: sllw a0, a0, a3
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: sw a0, 0(a2)
@@ -235,9 +225,7 @@ define signext i32 @ror_i32_neg_constant_rhs(i32 signext %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, -2
; RV64I-NEXT: neg a2, a0
-; RV64I-NEXT: andi a0, a0, 31
; RV64I-NEXT: srlw a0, a1, a0
-; RV64I-NEXT: andi a2, a2, 31
; RV64I-NEXT: sllw a1, a1, a2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
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