[llvm] [VPlan] Hook IR blocks into VPlan during skeleton creation (NFC) (PR #114292)

[via llvm-commits]

================
@@ -142,55 +142,88 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
 ; CHECK-NEXT:  LV: Interleaving is not beneficial.
 ; CHECK-NEXT:  LV: Found a vectorizable loop (vscale x 4) in <stdin>
 ; CHECK-NEXT:  LEV: Epilogue vectorization is not profitable for this loop
-; CHECK-NEXT:  Executing best plan with VF=vscale x 4, UF=1
+; CHECK:       Executing best plan with VF=vscale x 4, UF=1
 ; CHECK-NEXT:  VPlan 'Final VPlan for VF={vscale x 4},UF={1}' {
-; CHECK-NEXT:  Live-in vp<[[VF:%.+]]> = VF
-; CHECK-NEXT:  Live-in vp<[[VFxUF:%.+]]> = VF * UF
-; CHECK-NEXT:  Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
+; CHECK-NEXT:  Live-in ir<[[VF:%.+]]> = VF
+; CHECK-NEXT:  Live-in ir<[[VFxUF:%.+]]>.1 = VF * UF
+; CHECK-NEXT:  Live-in ir<[[VEC_TC:%.+]]> = vector-trip-count
 ; CHECK-NEXT:  vp<[[TC:%.+]]> = original trip-count
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  ir-bb<for.body.preheader>:
 ; CHECK-NEXT:    IR %0 = zext i32 %n to i64
 ; CHECK-NEXT:    EMIT vp<[[TC]]> = EXPAND SCEV (zext i32 %n to i64)
-; CHECK-NEXT:  No successors
+; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, ir-bb<vector.scevcheck>
 ; CHECK-EMPTY:
-; CHECK-NEXT:  vector.ph:
+; CHECK-NEXT:  ir-bb<vector.scevcheck>:
+; CHECK-NEXT:    IR   %3 = add nsw i64 %0, -1
+; CHECK-NEXT:    IR   %4 = add i32 %n, -1
+; CHECK-NEXT:    IR   %5 = trunc i64 %3 to i32
+; CHECK-NEXT:    IR   %mul = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 1, i32 %5)
+; CHECK-NEXT:    IR   %mul.result = extractvalue { i32, i1 } %mul, 0
+; CHECK-NEXT:    IR   %mul.overflow = extractvalue { i32, i1 } %mul, 1
+; CHECK-NEXT:    IR   %6 = sub i32 %4, %mul.result
+; CHECK-NEXT:    IR   %7 = icmp ugt i32 %6, %4
+; CHECK-NEXT:    IR   %8 = or i1 %7, %mul.overflow
+; CHECK-NEXT:    IR   %9 = icmp ugt i64 %3, 4294967295
+; CHECK-NEXT:    IR   %10 = or i1 %8, %9
+; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, ir-bb<vector.memcheck>
+; CHECK-EMPTY:
+; CHECK-NEXT:  ir-bb<vector.memcheck>:
+; CHECK-NEXT:    IR   %11 = call i64 @llvm.vscale.i64()
+; CHECK-NEXT:    IR   %12 = mul i64 %11, 4
+; CHECK-NEXT:    IR   %13 = mul i64 %12, 4
+; CHECK-NEXT:    IR   %14 = sub i64 %B1, %A2
+; CHECK-NEXT:    IR   %diff.check = icmp ult i64 %14, %13
+; CHECK-NEXT:  Successor(s): ir-bb<scalar.ph>, ir-bb<vector.ph>
+; CHECK-EMPTY:
+; CHECK-NEXT:  ir-bb<vector.ph>:
+; CHECK-NEXT:    IR   %15 = call i64 @llvm.vscale.i64()
+; CHECK-NEXT:    IR   %16 = mul i64 %15, 4
+; CHECK-NEXT:    IR   %n.mod.vf = urem i64 %0, %16
+; CHECK-NEXT:    IR   %n.vec = sub i64 %0, %n.mod.vf
+; CHECK-NEXT:    IR   %ind.end = sub i64 %0, %n.vec
+; CHECK-NEXT:    IR   %.cast = trunc i64 %n.vec to i32
+; CHECK-NEXT:    IR   %ind.end3 = sub i32 %n, %.cast
+; CHECK-NEXT:    IR   %17 = call i64 @llvm.vscale.i64()
+; CHECK-NEXT:    IR   %18 = mul i64 %17, 4
 ; CHECK-NEXT:  Successor(s): vector loop
 ; CHECK-EMPTY:
 ; CHECK-NEXT:  <x1> vector loop: {
 ; CHECK-NEXT:    vector.body:
-; CHECK-NEXT:      EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
+; CHECK-NEXT:      SCALAR-PHI vp<[[CAN_IV:%.+]]> = phi ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
----------------
ayalz wrote:

Ah, canonical induction conversion to scalar phi is another patch?

https://github.com/llvm/llvm-project/pull/114292