[llvm] [LoongArch] Enable `AllNBitUsers` checking for {DIV, MOD}.W{U} with div32 enabled (PR #118776)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-loongarch

Author: hev (heiher)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/118776.diff


2 Files Affected:

- (modified) llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp (+9-5) 
- (modified) llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll (+3-4) 


``````````diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp b/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
index ab90409fdf47d0..51e5e288a25124 100644
--- a/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
@@ -139,11 +139,6 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
       case LoongArch::MULH_WU:
       case LoongArch::MULW_D_W:
       case LoongArch::MULW_D_WU:
-      // TODO: {DIV,MOD}.{W,WU} consumes the upper 32 bits before LA664+.
-      // case LoongArch::DIV_W:
-      // case LoongArch::DIV_WU:
-      // case LoongArch::MOD_W:
-      // case LoongArch::MOD_WU:
       case LoongArch::SLL_W:
       case LoongArch::SLLI_W:
       case LoongArch::SRL_W:
@@ -170,6 +165,15 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
         if (Bits >= 32)
           break;
         return false;
+      // {DIV,MOD}.W{U} consumes the upper 32 bits if the div32
+      // feature is not enabled.
+      case LoongArch::DIV_W:
+      case LoongArch::DIV_WU:
+      case LoongArch::MOD_W:
+      case LoongArch::MOD_WU:
+        if (Bits >= 32 && ST.hasDiv32())
+          break;
+        return false;
       case LoongArch::MOVGR2CF:
         if (Bits >= 1)
           break;
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
index 7e7518154e8397..9276195b6fa0b4 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll
@@ -84,10 +84,9 @@ define signext i32 @sextw_rmv(i32 signext %a, i32 signext %b, i32 signext %c) {
 ;
 ; LA64-DIV32-LABEL: sextw_rmv:
 ; LA64-DIV32:       # %bb.0: # %entry
-; LA64-DIV32-NEXT:    mul.d $a0, $a1, $a0
-; LA64-DIV32-NEXT:    addi.w $a1, $a0, 0
-; LA64-DIV32-NEXT:    div.w $a0, $a2, $a0
-; LA64-DIV32-NEXT:    sltu $a0, $a0, $a1
+; LA64-DIV32-NEXT:    mul.w $a0, $a1, $a0
+; LA64-DIV32-NEXT:    div.w $a1, $a2, $a0
+; LA64-DIV32-NEXT:    sltu $a0, $a1, $a0
 ; LA64-DIV32-NEXT:    ret
 entry:
   %mul = mul nsw i32 %b, %a

``````````

</details>


https://github.com/llvm/llvm-project/pull/118776