[llvm] [AMDGPU][True16][CodeGen] support for true16 for vinterp 16bit instructions (PR #116702)

[Joe Nash via llvm-commits]

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@@ -181,9 +181,43 @@ multiclass VInterpF16Pat <SDPatternOperator op, Instruction inst,
   def : VInterpF16Pat<op, inst, dst_type, 1, high_pat>;
 }
 
+class VInterpF16Pat_t16 <SDPatternOperator op, Instruction inst,
+                     ValueType dstVT, bit high, bit isP2> : GCNPat <
+   (dstVT (op
+      (VINTERPMods f32:$src0, i32:$src0_modifiers),
+      (VINTERPMods f32:$src1, i32:$src1_modifiers),
+      (VINTERPMods f32:$src2, i32:$src2_modifiers),
+      !if(high, (i1 -1), (i1 0)))),
+    (inst $src0_modifiers,
+          (f16 (EXTRACT_SUBREG VGPR_32:$src0, !if(high, hi16, lo16))),
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Sisyph wrote:

Yes, I agree with @arsenm that these should have been 2 x half to begin with. However, I would be in favor of landing this patch as is, and adding a comment and filing an LLVM issue to change the intrinsic type. Since this is working for the current frontends it does not seem urgent to change the instrinsic.

https://github.com/llvm/llvm-project/pull/116702