[llvm] [AMDGPU] Handle hazard in v_scalef32_sr_fp4_* conversions (PR #118589)

[Matt Arsenault via llvm-commits]

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@@ -913,24 +913,31 @@ getDstSelForwardingOperand(const MachineInstr &MI, const GCNSubtarget &ST) {
   // (instructions with dest byte sel, e.g. CVT_SR_BF8_F32) and
   // op_sel[3:2]
   // != 0
-  if (SIInstrInfo::isSDWA(MI)) {
+  if (SIInstrInfo::isSDWA(MI))
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arsenm wrote:

Add braces

https://github.com/llvm/llvm-project/pull/118589