[llvm] [RISCV] Add software pipeliner support (PR #117546)

[Pengcheng Wang via llvm-commits]

================
@@ -4136,3 +4136,84 @@ bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
     return false;
   return LHS.getImm() <= RHS.getImm();
 }
+
+namespace {
+class RISCVPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
+  const MachineInstr *LHS;
+  const MachineInstr *RHS;
+  SmallVector<MachineOperand, 4> Cond;
+
+public:
+  RISCVPipelinerLoopInfo(const MachineInstr *LHS, const MachineInstr *RHS,
+                         const SmallVectorImpl<MachineOperand> &Cond)
+      : LHS(LHS), RHS(RHS), Cond(Cond.begin(), Cond.end()) {}
+
+  bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
+    // Make the instructions for loop control be placed in stage 0.
+    // The predecessors of LHS/RHS are considered by the caller.
+    if (LHS && MI == LHS)
----------------
wangpc-pp wrote:

It is the same, we just need a root SUnit and `SMSchedule::computeUnpipelineableNodes` will add all its predecessors.
https://github.com/llvm/llvm-project/blob/f947d5afd951fe0883e8afe2d00c00d6a97e29bd/llvm/lib/CodeGen/MachinePipeliner.cpp#L3172-L3196

So for AArch64, the LHS/RHS of the compare instruction will also be ignored, but not explicitly be ignored in `shouldIgnoreForPipelining`.

https://github.com/llvm/llvm-project/pull/117546