[llvm] [RISCV] Mark vmvNr.v as implicitly using vtype (PR #118414)

[Pengcheng Wang via llvm-commits]

wangpc-pp wrote:

> vmvNr no longer can be issued at the same cycle with the preceding vsetvli.

(Disclaimer: this is just my imagination, real microarchitecture may not be like this)
For this part, the hardware may issue vmvNr (using implementation-specific EEW, for example, EEW=8) before vtype is ready and check vill when committing. And also, there are some existing hardwares that don't trap.
What I am trying to say is, the modeling of side effect and instruction scheduling in compiler may differ from hardware behavior, and that may cause sub-optimal instruction sequences after scheduling. This may not be a big problem, we can revisit it if we do see some real issues it causes.

https://github.com/llvm/llvm-project/pull/118414