[llvm] f947d5a - [RISCV] Reduce redundancy in vnsrl tests

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2024-12-03T19:47:54-08:00
New Revision: f947d5afd951fe0883e8afe2d00c00d6a97e29bd

URL: https://github.com/llvm/llvm-project/commit/f947d5afd951fe0883e8afe2d00c00d6a97e29bd
DIFF: https://github.com/llvm/llvm-project/commit/f947d5afd951fe0883e8afe2d00c00d6a97e29bd.diff

LOG: [RISCV] Reduce redundancy in vnsrl tests

Triggered by discussion on pr118509.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
index 3aa16070470eaf..847ef9a7b36017 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
@@ -447,7 +447,6 @@ define void @vnsrl_0_i8_single_src(ptr %in, ptr %out) {
 ; V-NEXT:    vle8.v v8, (a0)
 ; V-NEXT:    vsetivli zero, 4, e8, mf8, ta, ma
 ; V-NEXT:    vnsrl.wi v8, v8, 0
-; V-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
 ; V-NEXT:    vse8.v v8, (a1)
 ; V-NEXT:    ret
 ;
@@ -457,18 +456,42 @@ define void @vnsrl_0_i8_single_src(ptr %in, ptr %out) {
 ; ZVE32F-NEXT:    vle8.v v8, (a0)
 ; ZVE32F-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
 ; ZVE32F-NEXT:    vnsrl.wi v8, v8, 0
+; ZVE32F-NEXT:    vse8.v v8, (a1)
+; ZVE32F-NEXT:    ret
+entry:
+  %0 = load <8 x i8>, ptr %in, align 1
+  %shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  store <4 x i8> %shuffle.i5, ptr %out, align 1
+  ret void
+}
+
+define void @vnsrl_8_i8_single_src(ptr %in, ptr %out) {
+; V-LABEL: vnsrl_8_i8_single_src:
+; V:       # %bb.0: # %entry
+; V-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
+; V-NEXT:    vle8.v v8, (a0)
+; V-NEXT:    vsetivli zero, 4, e8, mf8, ta, ma
+; V-NEXT:    vnsrl.wi v8, v8, 8
+; V-NEXT:    vse8.v v8, (a1)
+; V-NEXT:    ret
+;
+; ZVE32F-LABEL: vnsrl_8_i8_single_src:
+; ZVE32F:       # %bb.0: # %entry
 ; ZVE32F-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
+; ZVE32F-NEXT:    vle8.v v8, (a0)
+; ZVE32F-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; ZVE32F-NEXT:    vnsrl.wi v8, v8, 8
 ; ZVE32F-NEXT:    vse8.v v8, (a1)
 ; ZVE32F-NEXT:    ret
 entry:
   %0 = load <8 x i8>, ptr %in, align 1
-  %shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
-  store <8 x i8> %shuffle.i5, ptr %out, align 1
+  %shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+  store <4 x i8> %shuffle.i5, ptr %out, align 1
   ret void
 }
 
-define void @vnsrl_0_i8_single_src2(ptr %in, ptr %out) {
-; V-LABEL: vnsrl_0_i8_single_src2:
+define void @vnsrl_0_i8_single_wideuse(ptr %in, ptr %out) {
+; V-LABEL: vnsrl_0_i8_single_wideuse:
 ; V:       # %bb.0: # %entry
 ; V-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
 ; V-NEXT:    vle8.v v8, (a0)
@@ -478,7 +501,7 @@ define void @vnsrl_0_i8_single_src2(ptr %in, ptr %out) {
 ; V-NEXT:    vse8.v v8, (a1)
 ; V-NEXT:    ret
 ;
-; ZVE32F-LABEL: vnsrl_0_i8_single_src2:
+; ZVE32F-LABEL: vnsrl_0_i8_single_wideuse:
 ; ZVE32F:       # %bb.0: # %entry
 ; ZVE32F-NEXT:    vsetivli zero, 8, e8, mf4, ta, ma
 ; ZVE32F-NEXT:    vle8.v v8, (a0)