[llvm] deed1b0 - [SystemZ] Fix address parsing in HLASM mode

Ulrich Weigand via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 3 10:34:17 PST 2024


Author: Ulrich Weigand
Date: 2024-12-03T19:34:10+01:00
New Revision: deed1b0664e85cd3bb33451a81db52459d9f7663

URL: https://github.com/llvm/llvm-project/commit/deed1b0664e85cd3bb33451a81db52459d9f7663
DIFF: https://github.com/llvm/llvm-project/commit/deed1b0664e85cd3bb33451a81db52459d9f7663.diff

LOG: [SystemZ] Fix address parsing in HLASM mode

When parsing an address that contains only a single register
for an instruction that actually has both a base and an index
register, the parsed register is treated as base by AsmParser.

This is correct when emulating the GNU assembler, but not when
emulating HLASM, as the latter treat the register as index in
this case.

Added: 
    

Modified: 
    llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index e4aefc42d860f2..599afed2199fb7 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -1148,9 +1148,10 @@ ParseStatus SystemZAsmParser::parseAddress(OperandVector &Operands,
     if (HaveReg1) {
       if (parseAddressRegister(Reg1))
         return ParseStatus::Failure;
-      // If the are two registers, the first one is the index and the
-      // second is the base.
-      if (HaveReg2)
+      // If there are two registers, the first one is the index and the
+      // second is the base.  If there is only a single register, it is
+      // used as base with GAS and as index with HLASM.
+      if (HaveReg2 || isParsingHLASM())
         Index = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];
       else
         Base = Reg1.Num == 0 ? 0 : Regs[Reg1.Num];


        


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