[llvm] d1f4f63 - [SystemZ] Use nop mnemonics for disassembly
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 3 09:51:36 PST 2024
Author: Ulrich Weigand
Date: 2024-12-03T18:51:20+01:00
New Revision: d1f4f6368064d8d7bf09fbd5be8d74846d532c30
URL: https://github.com/llvm/llvm-project/commit/d1f4f6368064d8d7bf09fbd5be8d74846d532c30
DIFF: https://github.com/llvm/llvm-project/commit/d1f4f6368064d8d7bf09fbd5be8d74846d532c30.diff
LOG: [SystemZ] Use nop mnemonics for disassembly
To match the behavior of GNU binutils, output the nop family
of mnemonic aliases when disassembling.
Added:
Modified:
lld/test/ELF/systemz-gotent-relax-und-dso.s
lld/test/ELF/systemz-gotent-relax.s
lld/test/ELF/systemz-plt.s
lld/test/ELF/systemz-tls-gd.s
lld/test/ELF/systemz-tls-ld.s
llvm/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
llvm/test/MC/Disassembler/SystemZ/insns.txt
llvm/test/MC/SystemZ/insn-good-zos-pcrel.s
llvm/test/MC/SystemZ/insn-good.s
Removed:
################################################################################
diff --git a/lld/test/ELF/systemz-gotent-relax-und-dso.s b/lld/test/ELF/systemz-gotent-relax-und-dso.s
index 5a1bd7f949f897..e8b88056299cbf 100644
--- a/lld/test/ELF/systemz-gotent-relax-und-dso.s
+++ b/lld/test/ELF/systemz-gotent-relax-und-dso.s
@@ -14,9 +14,9 @@
# DISASM: Disassembly of section .text:
# DISASM-EMPTY:
# DISASM-NEXT: <foo>:
-# DISASM-NEXT: nop 0
+# DISASM-NEXT: nop
# DISASM: <hid>:
-# DISASM-NEXT: nop 0
+# DISASM-NEXT: nop
# DISASM: <_start>:
# DISASM-NEXT: lgrl %r1, 0x2400
# DISASM-NEXT: lgrl %r1, 0x2400
diff --git a/lld/test/ELF/systemz-gotent-relax.s b/lld/test/ELF/systemz-gotent-relax.s
index e84fd8d4653e9c..88b43a4e9d29cb 100644
--- a/lld/test/ELF/systemz-gotent-relax.s
+++ b/lld/test/ELF/systemz-gotent-relax.s
@@ -30,9 +30,9 @@
# DISASM: Disassembly of section .text:
# DISASM: 00000000010011e0 <foo>:
-# DISASM-NEXT: nop 0
+# DISASM-NEXT: nop
# DISASM: 00000000010011e4 <hid>:
-# DISASM-NEXT: nop 0
+# DISASM-NEXT: nop
# DISASM: 00000000010011e8 <ifunc>:
# DISASM-NEXT: br %r14
# DISASM: 00000000010011ea <_start>:
diff --git a/lld/test/ELF/systemz-plt.s b/lld/test/ELF/systemz-plt.s
index c7563cd18c2749..717343ce4c4d5a 100644
--- a/lld/test/ELF/systemz-plt.s
+++ b/lld/test/ELF/systemz-plt.s
@@ -48,9 +48,9 @@
# DIS-NEXT: 100102c: d2 07 f0 30 10 08 mvc 48(8,%r15), 8(%r1)
# DIS-NEXT: 1001032: e3 10 10 10 00 04 lg %r1, 16(%r1)
# DIS-NEXT: 1001038: 07 f1 br %r1
-# DIS-NEXT: 100103a: 07 00 nopr %r0
-# DIS-NEXT: 100103c: 07 00 nopr %r0
-# DIS-NEXT: 100103e: 07 00 nopr %r0
+# DIS-NEXT: 100103a: 07 00 nopr
+# DIS-NEXT: 100103c: 07 00 nopr
+# DIS-NEXT: 100103e: 07 00 nopr
# DIS-NEXT: 1001040: c0 10 00 00 10 54 larl %r1, 0x10030e8
# DIS-NEXT: 1001046: e3 10 10 00 00 04 lg %r1, 0(%r1)
# DIS-NEXT: 100104c: 07 f1 br %r1
diff --git a/lld/test/ELF/systemz-tls-gd.s b/lld/test/ELF/systemz-tls-gd.s
index 3976f55a6ae39e..742797e2d62e4f 100644
--- a/lld/test/ELF/systemz-tls-gd.s
+++ b/lld/test/ELF/systemz-tls-gd.s
@@ -58,17 +58,17 @@
## TP offset of a is at 0x1002218
# LE-NEXT: lgrl %r2, 0x1002218
-# LE-NEXT: brcl 0,
+# LE-NEXT: jgnop
# LE-NEXT: lgf %r2, 0(%r2,%r7)
## TP offset of b is at 0x1002220
# LE-NEXT: lgrl %r2, 0x1002220
-# LE-NEXT: brcl 0,
+# LE-NEXT: jgnop
# LE-NEXT: lgf %r2, 0(%r2,%r7)
## TP offset of c is at 0x1002228
# LE-NEXT: lgrl %r2, 0x1002228
-# LE-NEXT: brcl 0,
+# LE-NEXT: jgnop
# LE-NEXT: lgf %r2, 0(%r2,%r7)
## TP offsets
@@ -88,7 +88,7 @@
## TP offset of a is at 0x1002340
# IE-NEXT: lgrl %r2, 0x1002340
-# IE-NEXT: brcl 0,
+# IE-NEXT: jgnop
# IE-NEXT: lgf %r2, 0(%r2,%r7)
## GOT offset of the TP offset for b is at 0x1002348
diff --git a/lld/test/ELF/systemz-tls-ld.s b/lld/test/ELF/systemz-tls-ld.s
index 2cb36d7294f2b0..ef104b82644ce0 100644
--- a/lld/test/ELF/systemz-tls-ld.s
+++ b/lld/test/ELF/systemz-tls-ld.s
@@ -49,7 +49,7 @@
## GOT offset of the LDM TLS module ID is at 0x1002210
# LE-NEXT: lgrl %r2, 0x1002210
-# LE-NEXT: brcl 0,
+# LE-NEXT: jgnop
# LE-NEXT: la %r2, 0(%r2,%r7)
## TP offset for a is at 0x1002218
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 6e136b10aed428..ae8f669e9bab43 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -2328,6 +2328,12 @@ class AsmCondBranchRI<string mnemonic, bits<12> opcode>
: InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
mnemonic#"\t$M1, $RI2", []>;
+class NeverCondBranchRI<string mnemonic, bits<12> opcode>
+ : InstRIc<opcode, (outs), (ins brtarget16:$RI2),
+ mnemonic#"\t$RI2", []> {
+ let M1 = 0;
+}
+
class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
SDPatternOperator operator = null_frag>
: InstRIc<opcode, (outs), (ins brtarget16:$RI2),
@@ -2347,6 +2353,12 @@ class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
: InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
mnemonic#"\t$M1, $RI2", []>;
+class NeverCondBranchRIL<string mnemonic, bits<12> opcode>
+ : InstRILc<opcode, (outs), (ins brtarget32:$RI2),
+ mnemonic#"\t$RI2", []> {
+ let M1 = 0;
+}
+
class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
: InstRILc<opcode, (outs), (ins brtarget32:$RI2),
!subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
@@ -2365,10 +2377,16 @@ class AsmCondBranchRR<string mnemonic, bits<8> opcode>
: InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
mnemonic#"\t$R1, $R2", []>;
-class NeverCondBranchRR<string mnemonic, bits<8> opcode>
- : InstRR<opcode, (outs), (ins GR64:$R2),
- mnemonic#"\t$R2", []> {
- let R1 = 0;
+multiclass NeverCondBranchRR<string mnemonic, bits<8> opcode> {
+ // For the no-op (always false) branch, the target is optional.
+ def "" : InstRR<opcode, (outs), (ins GR64:$R2),
+ mnemonic#"\t$R2", []> {
+ let R1 = 0;
+ }
+ def Opt : InstRR<opcode, (outs), (ins), mnemonic, []> {
+ let R1 = 0;
+ let R2 = 0;
+ }
}
class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
@@ -2392,11 +2410,19 @@ class AsmCondBranchRX<string mnemonic, bits<8> opcode>
(ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$M1, $XBD2", []>;
-class NeverCondBranchRX<string mnemonic, bits<8> opcode>
- : InstRXb<opcode, (outs),
- (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
- mnemonic#"\t$XBD2", []> {
- let M1 = 0;
+multiclass NeverCondBranchRX<string mnemonic, bits<8> opcode> {
+ // For the no-op (always false) branch, the target is optional.
+ def "" : InstRXb<opcode, (outs),
+ (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ mnemonic#"\t$XBD2", []> {
+ let M1 = 0;
+ }
+ def Opt : InstRXb<opcode, (outs), (ins), mnemonic, []> {
+ let M1 = 0;
+ let B2 = 0;
+ let D2 = 0;
+ let X2 = 0;
+ }
}
class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index f3baf896658de5..5cbba0d9c5edd3 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -109,20 +109,11 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
}
// NOPs. These are again variants of the conditional branches, with the
-// condition mask set to "never". NOP_bare can't be an InstAlias since it
-// would need R0D hard coded which is not part of ADDR64BitRegClass.
-def NOP : NeverCondBranchRX<"nop", 0x47>;
-let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
- def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
-def NOPR : NeverCondBranchRR<"nopr", 0x07>;
-def NOPR_bare : InstAlias<"nopr", (NOPR R0D), 0>;
-
-// An alias of BRC 0, label
-def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>;
-
-// An alias of BRCL 0, label
-// jgnop on gnu ; jlnop on hlasm
-def JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>;
+// condition mask set to "never".
+defm NOP : NeverCondBranchRX<"nop", 0x47>;
+defm NOPR : NeverCondBranchRR<"nopr", 0x07>;
+def JNOP : NeverCondBranchRI<"jnop", 0xA74>;
+def JGNOP : NeverCondBranchRIL<"j{g|l}nop", 0xC04>;
// Fused compare-and-branch instructions.
//
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index d0fec02777875a..094b481b81f830 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -1557,7 +1557,7 @@ def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
// NOPs
//===----------------------------------------------------------------------===//
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
-
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?(Opt)?$")>;
+def : InstRW<[WLat1, VBU, NormalGr], (instregex "J(G)?NOP$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index a6d89ce9443c5a..b9376d422ded25 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -1647,7 +1647,7 @@ def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
// NOPs
//===----------------------------------------------------------------------===//
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
-
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?(Opt)?$")>;
+def : InstRW<[WLat1, VBU, NormalGr], (instregex "J(G)?NOP$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index 455354e283ad8e..5e28bf935a24b9 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -1694,6 +1694,7 @@ def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
// NOPs
//===----------------------------------------------------------------------===//
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?(Opt)?$")>;
+def : InstRW<[WLat1, VBU, NormalGr], (instregex "J(G)?NOP$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index 92abf0ba4022cc..2c01691707cc32 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -1727,6 +1727,7 @@ def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
// NOPs
//===----------------------------------------------------------------------===//
-def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?(Opt)?$")>;
+def : InstRW<[WLat1, VBU, NormalGr], (instregex "J(G)?NOP$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index 99d0d674bbbb2f..f41a7057bb1f66 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -1239,6 +1239,7 @@ def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
// NOPs
//===----------------------------------------------------------------------===//
-def : InstRW<[WLat1, LSU, EndGroup], (instregex "NOP(R)?$")>;
+def : InstRW<[WLat1, LSU, EndGroup], (instregex "NOP(R)?(Opt)?$")>;
+def : InstRW<[WLat1, LSU, EndGroup], (instregex "J(G)?NOP$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index 5b334da2bac342..8f0a10d2863a30 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -1284,6 +1284,7 @@ def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
// NOPs
//===----------------------------------------------------------------------===//
-def : InstRW<[WLat1, LSU, NormalGr], (instregex "NOP(R)?$")>;
+def : InstRW<[WLat1, LSU, NormalGr], (instregex "NOP(R)?(Opt)?$")>;
+def : InstRW<[WLat1, VBU, NormalGr], (instregex "J(G)?NOP$")>;
}
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt b/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
index ef1d0f1970d166..f12441c9c6cbaa 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns-pcrel.txt
@@ -52,7 +52,7 @@
0xa7 0xf5 0x7f 0xff
# 0x0000003c:
-# CHECK: brcl 0, 0x3c
+# CHECK: jgnop 0x3c
0xc0 0x04 0x00 0x00 0x00 0x00
# 0x00000042:
@@ -116,15 +116,15 @@
0xc0 0xf4 0x00 0x00 0x00 0x00
# 0x0000009c:
-# CHECK: brcl 0, 0x9a
+# CHECK: jgnop 0x9a
0xc0 0x04 0xff 0xff 0xff 0xff
# 0x000000a2:
-# CHECK: brcl 0, 0xffffffff000000a2
+# CHECK: jgnop 0xffffffff000000a2
0xc0 0x04 0x80 0x00 0x00 0x00
# 0x000000a8:
-# CHECK: brcl 0, 0x1000000a6
+# CHECK: jgnop 0x1000000a6
0xc0 0x04 0x7f 0xff 0xff 0xff
# 0x000000ae:
@@ -140,7 +140,7 @@
0xc0 0xf4 0x7f 0xff 0xff 0xff
# 0x000000c0:
-# CHECK: brc 0, 0xc0
+# CHECK: jnop 0xc0
0xa7 0x04 0x00 0x00
# 0x000000c4:
@@ -204,15 +204,15 @@
0xa7 0xf4 0x00 0x00
# 0x00000100:
-# CHECK: brc 0, 0xfe
+# CHECK: jnop 0xfe
0xa7 0x04 0xff 0xff
# 0x00000104:
-# CHECK: brc 0, 0xffffffffffff0104
+# CHECK: jnop 0xffffffffffff0104
0xa7 0x04 0x80 0x00
# 0x00000108:
-# CHECK: brc 0, 0x10106
+# CHECK: jnop 0x10106
0xa7 0x04 0x7f 0xff
# 0x0000010c:
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index 07a1ff6d183885..a4e4a2203a467f 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -1315,7 +1315,7 @@
# CHECK: bassm %r15, %r1
0x0c 0xf1
-# CHECK: nop 0
+# CHECK: nop
0x47 0x00 0x00 0x00
# CHECK: nop 4095
diff --git a/llvm/test/MC/SystemZ/insn-good-zos-pcrel.s b/llvm/test/MC/SystemZ/insn-good-zos-pcrel.s
index 734520798baa66..0acbe26d75b159 100644
--- a/llvm/test/MC/SystemZ/insn-good-zos-pcrel.s
+++ b/llvm/test/MC/SystemZ/insn-good-zos-pcrel.s
@@ -3,7 +3,7 @@
*CHECK: brcl 0, FOO * encoding: [0xc0,0x04,A,A,A,A]
*CHECK: fixup A - offset: 2, value: FOO+2, kind: FK_390_PC32DBL
-*CHECK: brcl 0, FOO * encoding: [0xc0,0x04,A,A,A,A]
+*CHECK: jgnop FOO * encoding: [0xc0,0x04,A,A,A,A]
*CHECK: fixup A - offset: 2, value: FOO+2, kind: FK_390_PC32DBL
brcl 0,FOO
jlnop FOO
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index 09f55049546c21..93f5ff27780ab9 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -1398,35 +1398,35 @@
#CHECK: brc 0, .[[LAB:L.*]]-65536 # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-65536)+2, kind: FK_390_PC16DBL
-#CHECK: brc 0, .[[LAB:L.*]]-65536 # encoding: [0xa7,0x04,A,A]
+#CHECK: jnop .[[LAB:L.*]]-65536 # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-65536)+2, kind: FK_390_PC16DBL
brc 0, -0x10000
jnop -0x10000
#CHECK: brc 0, .[[LAB:L.*]]-2 # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC16DBL
-#CHECK: brc 0, .[[LAB:L.*]]-2 # encoding: [0xa7,0x04,A,A]
+#CHECK: jnop .[[LAB:L.*]]-2 # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC16DBL
brc 0, -2
jnop -2
#CHECK: brc 0, .[[LAB:L.*]] # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL
-#CHECK: brc 0, .[[LAB:L.*]] # encoding: [0xa7,0x04,A,A]
+#CHECK: jnop .[[LAB:L.*]] # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL
brc 0, 0
jnop 0
#CHECK: brc 0, .[[LAB:L.*]]+65534 # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL
-#CHECK: brc 0, .[[LAB:L.*]]+65534 # encoding: [0xa7,0x04,A,A]
+#CHECK: jnop .[[LAB:L.*]]+65534 # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL
brc 0, 0xfffe
jnop 0xfffe
#CHECK: brc 0, foo # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
-#CHECK: brc 0, foo # encoding: [0xa7,0x04,A,A]
+#CHECK: jnop foo # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL
brc 0, foo
jnop foo
@@ -1623,7 +1623,7 @@
#CHECK: brc 0, bar+100 # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL
-#CHECK: brc 0, bar+100 # encoding: [0xa7,0x04,A,A]
+#CHECK: jnop bar+100 # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL
brc 0, bar+100
jnop bar+100
@@ -1735,7 +1735,7 @@
#CHECK: brc 0, bar at PLT # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: bar at PLT+2, kind: FK_390_PC16DBL
-#CHECK: brc 0, bar at PLT # encoding: [0xa7,0x04,A,A]
+#CHECK: jnop bar at PLT # encoding: [0xa7,0x04,A,A]
#CHECK: fixup A - offset: 2, value: bar at PLT+2, kind: FK_390_PC16DBL
brc 0, bar at PLT
jnop bar at PLT
@@ -1847,32 +1847,32 @@
#CHECK: brcl 0, .[[LAB:L.*]]-4294967296 # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL
-#CHECK: brcl 0, .[[LAB:L.*]]-4294967296 # encoding: [0xc0,0x04,A,A,A,A]
+#CHECK: jgnop .[[LAB:L.*]]-4294967296 # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL
brcl 0, -0x100000000
jgnop -0x100000000
#CHECK: brcl 0, .[[LAB:L.*]]-2 # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL
-#CHECK: brcl 0, .[[LAB:L.*]]-2 # encoding: [0xc0,0x04,A,A,A,A]
+#CHECK: jgnop .[[LAB:L.*]]-2 # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC32DBL
brcl 0, -2
jgnop -2
#CHECK: brcl 0, .[[LAB:L.*]] # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL
-#CHECK: brcl 0, .[[LAB:L.*]] # encoding: [0xc0,0x04,A,A,A,A]
+#CHECK: jgnop .[[LAB:L.*]] # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC32DBL
brcl 0, 0
jgnop 0
#CHECK: brcl 0, .[[LAB:L.*]]+4294967294 # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL
-#CHECK: brcl 0, .[[LAB:L.*]]+4294967294 # encoding: [0xc0,0x04,A,A,A,A]
+#CHECK: jgnop .[[LAB:L.*]]+4294967294 # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (.[[LAB]]+4294967294)+2, kind: FK_390_PC32DBL
brcl 0, 0xfffffffe
jgnop 0xfffffffe
#CHECK: brcl 0, foo # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL
-#CHECK: brcl 0, foo # encoding: [0xc0,0x04,A,A,A,A]
+#CHECK: jgnop foo # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL
brcl 0, foo
jgnop foo
@@ -2065,7 +2065,7 @@
#CHECK: brcl 0, bar+100 # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL
-#CHECK: brcl 0, bar+100 # encoding: [0xc0,0x04,A,A,A,A]
+#CHECK: jgnop bar+100 # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL
brcl 0, bar+100
jgnop bar+100
@@ -2177,7 +2177,7 @@
#CHECK: brcl 0, bar at PLT # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: bar at PLT+2, kind: FK_390_PC32DBL
-#CHECK: brcl 0, bar at PLT # encoding: [0xc0,0x04,A,A,A,A]
+#CHECK: jgnop bar at PLT # encoding: [0xc0,0x04,A,A,A,A]
#CHECK: fixup A - offset: 2, value: bar at PLT+2, kind: FK_390_PC32DBL
brcl 0, bar at PLT
jgnop bar at PLT
@@ -13142,7 +13142,7 @@
#CHECK: nop 0 # encoding: [0x47,0x00,0x00,0x00]
#CHECK: nop # encoding: [0x47,0x00,0x00,0x00]
#CHECK: nopr %r7 # encoding: [0x07,0x07]
-#CHECK: nopr %r0 # encoding: [0x07,0x00]
+#CHECK: nopr # encoding: [0x07,0x00]
nop 0
nop
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