[llvm] [RISCV] Add software pipeliner support (PR #117546)

[Min-Yih Hsu via llvm-commits]

mshockwave wrote:

> > Out of curiosity, have you seen any benefits of adding and enabling this support?
> 
> I haven't tried current implementation, but we did implement it and saw very small performance gain on an OoO core before (that was about 3 years ago, on LLVM 13). Situation may have changed during these years and AArch64 added this support recently (about one year ago, not that _recently_) and disabled it by default. It seems some ARM cores can benefit from it (see also #79589). 

I'm a little surprised to find that this might benefit out-of-order cores -- I thought in-order cores will most likely be the one that gain improvements from this, if there is any. Theoretically, OoO cores can already look into future loop iterations thus overlapping several iterations via software pipelining doesn't always make a difference. That said, the size of hardware scheduler buffers might be a limiting factors (on how far the HW can look ahead) and maybe that's why AArch64 still see performance improvement. But I would like to point out that they also saw "significant performance degradation" in some cases without specifying the quantities nor showing the average percentage of performance changes across all benchmarks. So personally I'll be more cautious on this and I agree that we should turn this feature off by default.

https://github.com/llvm/llvm-project/pull/117546