[llvm] [RISCV] Clear vill for whole vector register moves in vsetvli insertion (PR #118283)

[Philip Reames via llvm-commits]

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@@ -1426,6 +1468,15 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
       PrefixTransparent = false;
     }
 
+    if (isVectorCopy(ST->getRegisterInfo(), MI)) {
+      if (!PrevInfo.isCompatible(DemandedFields::all(), CurInfo, LIS)) {
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preames wrote:

As a followup, we can reduce the number of vsetvli's emitted by integrating this with the needVSETVLIPHI logic below.  Definitely non blocking.  

https://github.com/llvm/llvm-project/pull/118283