[llvm] [RISCV] Clear vill for whole vector register moves in vsetvli insertion (PR #118283)

[Philip Reames via llvm-commits]

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@@ -503,6 +517,21 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
     }
   }
 
+  // In §32.16.6, whole vector register moves have a dependency on SEW. At the
+  // MIR level though we don't encode the element type, and it gives the same
+  // result whatever the SEW may be.
+  //
+  // However it does need valid SEW, i.e. vill must be cleared. The entry to a
+  // function, calls and inline assembly may all set it, so make sure we clear
+  // it for whole register copies. Do this by leaving VILL demanded.
+  if (isVectorCopy(ST->getRegisterInfo(), MI)) {
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preames wrote:

Can you add a cl::opt for testing?  I think simple having it conditional here would effectively disable this change, and having a quick way to rule in/out this change might be useful going forward.

https://github.com/llvm/llvm-project/pull/118283