[llvm] [CodeGen] [AMDGPU] Attempt DAGCombine for fmul with select to ldexp (PR #111109)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 3 02:00:56 PST 2024
================
@@ -14595,6 +14596,70 @@ SDValue SITargetLowering::performFDivCombine(SDNode *N,
return SDValue();
}
+SDValue SITargetLowering::performFMulCombine(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ SelectionDAG &DAG = DCI.DAG;
+ EVT VT = N->getValueType(0);
+ EVT scalarVT = VT.getScalarType();
+ EVT IntVT = VT.changeElementType(MVT::i32);
+
+ SDLoc SL(N);
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+
+ SDNodeFlags Flags = N->getFlags();
+ SDNodeFlags LHSFlags = LHS->getFlags();
+
+ // It is cheaper to realize i32 inline constants as compared against
+ // as materializing f16 or f64 (or even non-inline f32) values,
+ // possible via ldexp usage, as shown below :
+ //
+ // Given : A = 2^a & B = 2^b ; where a and b are integers.
+ // fmul x, (select y, A, B) -> ldexp( x, (select i32 y, a, b) )
+ // fmul x, (select y, -A, -B) -> ldexp( (fneg x), (select i32 y, a, b) )
+ if (scalarVT == MVT::f64 || scalarVT == MVT::f32 || scalarVT == MVT::f16) {
+ if (RHS.hasOneUse() && RHS.getOpcode() == ISD::SELECT) {
+ const ConstantFPSDNode *TrueNode =
+ isConstOrConstSplatFP(RHS.getOperand(1));
+ if (!TrueNode)
+ return SDValue();
+ const ConstantFPSDNode *FalseNode =
+ isConstOrConstSplatFP(RHS.getOperand(2));
+ if (!FalseNode)
+ return SDValue();
+
+ if (TrueNode->isNegative() != FalseNode->isNegative())
+ return SDValue();
+
+ // For f32, only non-inline constants should be transformed.
+ const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
+ if (scalarVT == MVT::f32 &&
+ TII->isInlineConstant(TrueNode->getValueAPF()) &&
+ TII->isInlineConstant(FalseNode->getValueAPF()))
+ return SDValue();
+
+ LHS = TrueNode->isNegative()
+ ? DAG.getNode(ISD::FNEG, SL, VT, LHS, LHSFlags)
----------------
jayfoad wrote:
Sink this getNode call after the checks below that can bail out.
https://github.com/llvm/llvm-project/pull/111109
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