[llvm] [ValueTracking] Infer NonEqual from dominating conditions/assumptions (PR #117442)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 2 23:08:03 PST 2024
https://github.com/dtcxzyw updated https://github.com/llvm/llvm-project/pull/117442
>From 8584ea69d2f4ed965dd2e9d82ccb73cc9c226031 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Sun, 24 Nov 2024 00:09:52 +0800
Subject: [PATCH 1/4] [InstCombine] Add pre-commit tests. NFC.
---
llvm/test/Transforms/InstCombine/icmp-dom.ll | 212 +++++++++++++++++++
1 file changed, 212 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/icmp-dom.ll b/llvm/test/Transforms/InstCombine/icmp-dom.ll
index 3cf3a7af77041c..ab3bf511ab2904 100644
--- a/llvm/test/Transforms/InstCombine/icmp-dom.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-dom.ll
@@ -534,3 +534,215 @@ else:
%cmp1 = icmp eq i32 %and1, 0
ret i1 %cmp1
}
+
+; TODO: X != Y implies X | Y != 0
+define i1 @or_nonzero_from_nonequal(i8 %x, i8 %y) {
+; CHECK-LABEL: @or_nonzero_from_nonequal(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[COND:%.*]] = icmp eq i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: br i1 [[COND]], label [[IF_ELSE:%.*]], label [[IF_THEN:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[OR:%.*]] = or i8 [[X]], [[Y]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[OR]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK: if.else:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %cond = icmp eq i8 %x, %y
+ br i1 %cond, label %if.else, label %if.then
+
+if.then:
+ %or = or i8 %x, %y
+ %cmp = icmp eq i8 %or, 0
+ ret i1 %cmp
+
+if.else:
+ ret i1 false
+}
+
+define i1 @test_nonequal_domcond1(i64 %x, i64 %y, i64 %z, i64 %w) {
+; CHECK-LABEL: @test_nonequal_domcond1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[COND1:%.*]] = icmp eq i64 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[COND2:%.*]] = icmp eq i64 [[W:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[COND1]], i1 true, i1 [[COND2]]
+; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[SUB1:%.*]] = sub i64 [[W]], [[Z]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub i64 [[Y]], [[X]]
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SUB1]], i64 [[SUB2]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[UMIN]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK: if.end:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %cond1 = icmp eq i64 %y, %x
+ %cond2 = icmp eq i64 %w, %z
+ %or.cond = select i1 %cond1, i1 true, i1 %cond2
+ br i1 %or.cond, label %if.end, label %if.then
+
+if.then:
+ %sub1 = sub i64 %w, %z
+ %sub2 = sub i64 %y, %x
+ %umin = call i64 @llvm.umin.i64(i64 %sub1, i64 %sub2)
+ %cmp = icmp eq i64 %umin, 0
+ ret i1 %cmp
+
+if.end:
+ ret i1 false
+}
+
+define i1 @test_nonequal_domcond2(i64 %x, i64 %y, i64 %z, i64 %w) {
+; CHECK-LABEL: @test_nonequal_domcond2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[COND1:%.*]] = icmp ne i64 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[COND2:%.*]] = icmp ne i64 [[W:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[COND1]], i1 [[COND2]], i1 false
+; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: [[SUB1:%.*]] = sub i64 [[W]], [[Z]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub i64 [[Y]], [[X]]
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SUB1]], i64 [[SUB2]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[UMIN]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK: if.end:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %cond1 = icmp ne i64 %y, %x
+ %cond2 = icmp ne i64 %w, %z
+ %or.cond = select i1 %cond1, i1 %cond2, i1 false
+ br i1 %or.cond, label %if.then, label %if.end
+
+if.then:
+ %sub1 = sub i64 %w, %z
+ %sub2 = sub i64 %y, %x
+ %umin = call i64 @llvm.umin.i64(i64 %sub1, i64 %sub2)
+ %cmp = icmp eq i64 %umin, 0
+ ret i1 %cmp
+
+if.end:
+ ret i1 false
+}
+
+define i1 @test_nonequal_assume(i64 %x, i64 %y, i64 %z, i64 %w) {
+; CHECK-LABEL: @test_nonequal_assume(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[COND1:%.*]] = icmp ne i64 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: call void @llvm.assume(i1 [[COND1]])
+; CHECK-NEXT: [[COND2:%.*]] = icmp ne i64 [[W:%.*]], [[Z:%.*]]
+; CHECK-NEXT: call void @llvm.assume(i1 [[COND2]])
+; CHECK-NEXT: [[SUB1:%.*]] = sub i64 [[W]], [[Z]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub i64 [[Y]], [[X]]
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SUB1]], i64 [[SUB2]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[UMIN]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+entry:
+ %cond1 = icmp ne i64 %y, %x
+ call void @llvm.assume(i1 %cond1)
+ %cond2 = icmp ne i64 %w, %z
+ call void @llvm.assume(i1 %cond2)
+
+ %sub1 = sub i64 %w, %z
+ %sub2 = sub i64 %y, %x
+ %umin = call i64 @llvm.umin.i64(i64 %sub1, i64 %sub2)
+ %cmp = icmp eq i64 %umin, 0
+ ret i1 %cmp
+}
+
+; Negative tests
+
+define i1 @test_nonequal_invalid_domcond1(i64 %x, i64 %y, i64 %z, i64 %w) {
+; CHECK-LABEL: @test_nonequal_invalid_domcond1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[COND1:%.*]] = icmp ne i64 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[COND2:%.*]] = icmp eq i64 [[W:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[COND1]], i1 true, i1 [[COND2]]
+; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: ret i1 true
+; CHECK: if.end:
+; CHECK-NEXT: ret i1 false
+;
+entry:
+ %cond1 = icmp ne i64 %y, %x
+ %cond2 = icmp eq i64 %w, %z
+ %or.cond = select i1 %cond1, i1 true, i1 %cond2
+ br i1 %or.cond, label %if.end, label %if.then
+
+if.then:
+ %sub1 = sub i64 %w, %z
+ %sub2 = sub i64 %y, %x
+ %umin = call i64 @llvm.umin.i64(i64 %sub1, i64 %sub2)
+ %cmp = icmp eq i64 %umin, 0
+ ret i1 %cmp
+
+if.end:
+ ret i1 false
+}
+
+define i1 @test_nonequal_invalid_domcond2(i64 %x, i64 %y, i64 %z, i64 %w) {
+; CHECK-LABEL: @test_nonequal_invalid_domcond2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[COND1:%.*]] = icmp eq i64 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[COND2:%.*]] = icmp eq i64 [[W:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[COND1]], i1 true, i1 [[COND2]]
+; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK: if.then:
+; CHECK-NEXT: br label [[IF_END]]
+; CHECK: if.end:
+; CHECK-NEXT: [[SUB1:%.*]] = sub i64 [[W]], [[Z]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub i64 [[Y]], [[X]]
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SUB1]], i64 [[SUB2]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[UMIN]], 0
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+entry:
+ %cond1 = icmp eq i64 %y, %x
+ %cond2 = icmp eq i64 %w, %z
+ %or.cond = select i1 %cond1, i1 true, i1 %cond2
+ br i1 %or.cond, label %if.then, label %if.end
+
+if.then:
+ br label %if.end
+
+if.end:
+ %sub1 = sub i64 %w, %z
+ %sub2 = sub i64 %y, %x
+ %umin = call i64 @llvm.umin.i64(i64 %sub1, i64 %sub2)
+ %cmp = icmp eq i64 %umin, 0
+ ret i1 %cmp
+}
+
+define i1 @test_nonequal_invalid_assume(i64 %x, i64 %y, i64 %z, i64 %w) {
+; CHECK-LABEL: @test_nonequal_invalid_assume(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[SUB1:%.*]] = sub i64 [[W:%.*]], [[Z:%.*]]
+; CHECK-NEXT: [[SUB2:%.*]] = sub i64 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SUB1]], i64 [[SUB2]])
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[UMIN]], 0
+; CHECK-NEXT: call void @side_effect()
+; CHECK-NEXT: [[COND1:%.*]] = icmp ne i64 [[Y]], [[X]]
+; CHECK-NEXT: call void @llvm.assume(i1 [[COND1]])
+; CHECK-NEXT: [[COND2:%.*]] = icmp ne i64 [[W]], [[Z]]
+; CHECK-NEXT: call void @llvm.assume(i1 [[COND2]])
+; CHECK-NEXT: ret i1 [[CMP]]
+;
+entry:
+ %sub1 = sub i64 %w, %z
+ %sub2 = sub i64 %y, %x
+ %umin = call i64 @llvm.umin.i64(i64 %sub1, i64 %sub2)
+ %cmp = icmp eq i64 %umin, 0
+
+ call void @side_effect()
+ %cond1 = icmp ne i64 %y, %x
+ call void @llvm.assume(i1 %cond1)
+ %cond2 = icmp ne i64 %w, %z
+ call void @llvm.assume(i1 %cond2)
+ ret i1 %cmp
+}
+
+declare void @side_effect()
>From 551aebdb198d11711ac704a67a0f489280b8415e Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Sun, 24 Nov 2024 00:26:40 +0800
Subject: [PATCH 2/4] [ValueTracking] Infer NonEqual from dominating
conditions/assumptions
---
llvm/lib/Analysis/ValueTracking.cpp | 49 +++++++++++++++++++-
llvm/test/Transforms/InstCombine/icmp-dom.ll | 18 ++-----
2 files changed, 50 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index c48068afc04816..f08ec596899bb4 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -3748,6 +3748,50 @@ static bool isKnownNonEqual(const Value *V1, const Value *V2,
match(V2, m_PtrToIntSameSize(Q.DL, m_Value(B))))
return isKnownNonEqual(A, B, DemandedElts, Depth + 1, Q);
+ if (!Q.CxtI)
+ return false;
+
+ // Try to infer NonEqual based on information from dominating conditions.
+ if (Q.DC && Q.DT) {
+ for (BranchInst *BI : Q.DC->conditionsFor(V1)) {
+ Value *Cond = BI->getCondition();
+ BasicBlockEdge Edge0(BI->getParent(), BI->getSuccessor(0));
+ if (isImpliedCondition(Cond, ICmpInst::ICMP_NE, V1, V2, Q.DL,
+ /*LHSIsTrue=*/true, Depth)
+ .value_or(false) &&
+ Q.DT->dominates(Edge0, Q.CxtI->getParent()))
+ return true;
+
+ BasicBlockEdge Edge1(BI->getParent(), BI->getSuccessor(1));
+ if (isImpliedCondition(Cond, ICmpInst::ICMP_NE, V1, V2, Q.DL,
+ /*LHSIsTrue=*/false, Depth)
+ .value_or(false) &&
+ Q.DT->dominates(Edge1, Q.CxtI->getParent()))
+ return true;
+ }
+ }
+
+ if (!Q.AC)
+ return false;
+
+ // Try to infer NonEqual based on information from assumptions.
+ for (auto &AssumeVH : Q.AC->assumptionsFor(V1)) {
+ if (!AssumeVH)
+ continue;
+ CallInst *I = cast<CallInst>(AssumeVH);
+
+ assert(I->getFunction() == Q.CxtI->getFunction() &&
+ "Got assumption for the wrong function!");
+ assert(I->getIntrinsicID() == Intrinsic::assume &&
+ "must be an assume intrinsic");
+
+ if (isImpliedCondition(I->getArgOperand(0), ICmpInst::ICMP_NE, V1, V2, Q.DL,
+ /*LHSIsTrue=*/true, Depth)
+ .value_or(false) &&
+ isValidAssumeForContext(I, Q.CxtI, Q.DT))
+ return true;
+ }
+
return false;
}
@@ -10037,10 +10081,10 @@ void llvm::findValuesAffectedByCondition(
Worklist.push_back(B);
}
} else if (match(V, m_ICmp(Pred, m_Value(A), m_Value(B)))) {
- AddCmpOperands(A, B);
-
bool HasRHSC = match(B, m_ConstantInt());
if (ICmpInst::isEquality(Pred)) {
+ AddAffected(A);
+ AddAffected(B);
if (HasRHSC) {
Value *Y;
// (X & C) or (X | C) or (X ^ C).
@@ -10055,6 +10099,7 @@ void llvm::findValuesAffectedByCondition(
}
}
} else {
+ AddCmpOperands(A, B);
if (HasRHSC) {
// Handle (A + C1) u< C2, which is the canonical form of
// A > C3 && A < C4.
diff --git a/llvm/test/Transforms/InstCombine/icmp-dom.ll b/llvm/test/Transforms/InstCombine/icmp-dom.ll
index ab3bf511ab2904..07793e8951de59 100644
--- a/llvm/test/Transforms/InstCombine/icmp-dom.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-dom.ll
@@ -569,11 +569,7 @@ define i1 @test_nonequal_domcond1(i64 %x, i64 %y, i64 %z, i64 %w) {
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[COND1]], i1 true, i1 [[COND2]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: [[SUB1:%.*]] = sub i64 [[W]], [[Z]]
-; CHECK-NEXT: [[SUB2:%.*]] = sub i64 [[Y]], [[X]]
-; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SUB1]], i64 [[SUB2]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[UMIN]], 0
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: ret i1 false
; CHECK: if.end:
; CHECK-NEXT: ret i1 false
;
@@ -602,11 +598,7 @@ define i1 @test_nonequal_domcond2(i64 %x, i64 %y, i64 %z, i64 %w) {
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[COND1]], i1 [[COND2]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: [[SUB1:%.*]] = sub i64 [[W]], [[Z]]
-; CHECK-NEXT: [[SUB2:%.*]] = sub i64 [[Y]], [[X]]
-; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SUB1]], i64 [[SUB2]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[UMIN]], 0
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: ret i1 false
; CHECK: if.end:
; CHECK-NEXT: ret i1 false
;
@@ -634,11 +626,7 @@ define i1 @test_nonequal_assume(i64 %x, i64 %y, i64 %z, i64 %w) {
; CHECK-NEXT: call void @llvm.assume(i1 [[COND1]])
; CHECK-NEXT: [[COND2:%.*]] = icmp ne i64 [[W:%.*]], [[Z:%.*]]
; CHECK-NEXT: call void @llvm.assume(i1 [[COND2]])
-; CHECK-NEXT: [[SUB1:%.*]] = sub i64 [[W]], [[Z]]
-; CHECK-NEXT: [[SUB2:%.*]] = sub i64 [[Y]], [[X]]
-; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[SUB1]], i64 [[SUB2]])
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[UMIN]], 0
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: ret i1 false
;
entry:
%cond1 = icmp ne i64 %y, %x
>From d6fad59c9dd4ea38f8fa0a9b10225d82277c5534 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Sun, 24 Nov 2024 00:27:53 +0800
Subject: [PATCH 3/4] [ValueTracking] Adjust evaluation order
---
llvm/lib/Analysis/ValueTracking.cpp | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index f08ec596899bb4..b45bfa2fd3d964 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -3756,17 +3756,17 @@ static bool isKnownNonEqual(const Value *V1, const Value *V2,
for (BranchInst *BI : Q.DC->conditionsFor(V1)) {
Value *Cond = BI->getCondition();
BasicBlockEdge Edge0(BI->getParent(), BI->getSuccessor(0));
- if (isImpliedCondition(Cond, ICmpInst::ICMP_NE, V1, V2, Q.DL,
+ if (Q.DT->dominates(Edge0, Q.CxtI->getParent()) &&
+ isImpliedCondition(Cond, ICmpInst::ICMP_NE, V1, V2, Q.DL,
/*LHSIsTrue=*/true, Depth)
- .value_or(false) &&
- Q.DT->dominates(Edge0, Q.CxtI->getParent()))
+ .value_or(false))
return true;
BasicBlockEdge Edge1(BI->getParent(), BI->getSuccessor(1));
- if (isImpliedCondition(Cond, ICmpInst::ICMP_NE, V1, V2, Q.DL,
+ if (Q.DT->dominates(Edge1, Q.CxtI->getParent()) &&
+ isImpliedCondition(Cond, ICmpInst::ICMP_NE, V1, V2, Q.DL,
/*LHSIsTrue=*/false, Depth)
- .value_or(false) &&
- Q.DT->dominates(Edge1, Q.CxtI->getParent()))
+ .value_or(false))
return true;
}
}
>From 8f3cf204bb91ce09fb3651b8a7e770de7e603b2f Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 3 Dec 2024 15:06:38 +0800
Subject: [PATCH 4/4] [ValueTracking] Convert `isKnownNonEqual` to use
`SimplifyQuery`
---
llvm/include/llvm/Analysis/ValueTracking.h | 7 ++-----
llvm/lib/Analysis/BasicAliasAnalysis.cpp | 4 ++--
llvm/lib/Analysis/InstructionSimplify.cpp | 2 +-
llvm/lib/Analysis/ValueTracking.cpp | 9 +++------
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp | 2 +-
llvm/test/Transforms/InstCombine/known-bits.ll | 6 +-----
6 files changed, 10 insertions(+), 20 deletions(-)
diff --git a/llvm/include/llvm/Analysis/ValueTracking.h b/llvm/include/llvm/Analysis/ValueTracking.h
index 2b0377903ac8e3..f42d392695d6d9 100644
--- a/llvm/include/llvm/Analysis/ValueTracking.h
+++ b/llvm/include/llvm/Analysis/ValueTracking.h
@@ -164,11 +164,8 @@ bool isKnownNegative(const Value *V, const SimplifyQuery &DL,
/// Return true if the given values are known to be non-equal when defined.
/// Supports scalar integer types only.
-bool isKnownNonEqual(const Value *V1, const Value *V2, const DataLayout &DL,
- AssumptionCache *AC = nullptr,
- const Instruction *CxtI = nullptr,
- const DominatorTree *DT = nullptr,
- bool UseInstrInfo = true);
+bool isKnownNonEqual(const Value *V1, const Value *V2, const SimplifyQuery &SQ,
+ unsigned Depth = 0);
/// Return true if 'V & Mask' is known to be zero. We use this predicate to
/// simplify operations downstream. Mask is known to be zero for bits that V
diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
index 381fb7bbdb5171..86c758864828df 100644
--- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp
+++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
@@ -1369,8 +1369,8 @@ AliasResult BasicAAResult::aliasGEP(
const VariableGEPIndex &Var1 = DecompGEP1.VarIndices[1];
if (Var0.hasNegatedScaleOf(Var1) && Var0.Val.TruncBits == 0 &&
Var0.Val.hasSameCastsAs(Var1.Val) && !AAQI.MayBeCrossIteration &&
- isKnownNonEqual(Var0.Val.V, Var1.Val.V, DL, &AC, /* CxtI */ nullptr,
- DT))
+ isKnownNonEqual(Var0.Val.V, Var1.Val.V,
+ SimplifyQuery(DL, DT, &AC, /*CxtI=*/nullptr)))
MinAbsVarIndex = Var0.Scale.abs();
}
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp
index 01b0a089aab718..0938ee1cce84ed 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -4014,7 +4014,7 @@ static Value *simplifyICmpInst(unsigned Predicate, Value *LHS, Value *RHS,
// This is potentially expensive, and we have already computedKnownBits for
// compares with 0 above here, so only try this for a non-zero compare.
if (ICmpInst::isEquality(Pred) && !match(RHS, m_Zero()) &&
- isKnownNonEqual(LHS, RHS, Q.DL, Q.AC, Q.CxtI, Q.DT, Q.IIQ.UseInstrInfo)) {
+ isKnownNonEqual(LHS, RHS, Q)) {
return Pred == ICmpInst::ICMP_NE ? getTrue(ITy) : getFalse(ITy);
}
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index b45bfa2fd3d964..a1c28a69b9be1e 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -303,18 +303,15 @@ static bool isKnownNonEqual(const Value *V1, const Value *V2,
const SimplifyQuery &Q);
bool llvm::isKnownNonEqual(const Value *V1, const Value *V2,
- const DataLayout &DL, AssumptionCache *AC,
- const Instruction *CxtI, const DominatorTree *DT,
- bool UseInstrInfo) {
+ const SimplifyQuery &Q, unsigned Depth) {
// We don't support looking through casts.
if (V1 == V2 || V1->getType() != V2->getType())
return false;
auto *FVTy = dyn_cast<FixedVectorType>(V1->getType());
APInt DemandedElts =
FVTy ? APInt::getAllOnes(FVTy->getNumElements()) : APInt(1, 1);
- return ::isKnownNonEqual(
- V1, V2, DemandedElts, 0,
- SimplifyQuery(DL, DT, AC, safeCxtI(V2, V1, CxtI), UseInstrInfo));
+ return ::isKnownNonEqual(V1, V2, DemandedElts, Depth,
+ Q.getWithInstruction(safeCxtI(V2, V1, Q.CxtI)));
}
bool llvm::MaskedValueIsZero(const Value *V, const APInt &Mask,
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index fed21db393ed22..ab0cb709a2b91e 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -5343,7 +5343,7 @@ Instruction *InstCombinerImpl::foldICmpBinOp(ICmpInst &I,
if (ICmpInst::isEquality(Pred)) {
// If X != Y, fold (X *nw Z) eq/ne (Y *nw Z) -> Z eq/ne 0
if (((Op0HasNSW && Op1HasNSW) || (Op0HasNUW && Op1HasNUW)) &&
- isKnownNonEqual(X, Y, DL, &AC, &I, &DT))
+ isKnownNonEqual(X, Y, SQ))
return new ICmpInst(Pred, Z, Constant::getNullValue(Z->getType()));
KnownBits ZKnown = computeKnownBits(Z, 0, &I);
diff --git a/llvm/test/Transforms/InstCombine/known-bits.ll b/llvm/test/Transforms/InstCombine/known-bits.ll
index 9467f507cd6306..bd6b2f015145e5 100644
--- a/llvm/test/Transforms/InstCombine/known-bits.ll
+++ b/llvm/test/Transforms/InstCombine/known-bits.ll
@@ -1609,17 +1609,13 @@ if.else:
ret i16 0
}
-; TODO: %cmp always evaluates to false
-
define i1 @test_simplify_icmp2(double %x) {
; CHECK-LABEL: @test_simplify_icmp2(
; CHECK-NEXT: [[ABS:%.*]] = tail call double @llvm.fabs.f64(double [[X:%.*]])
; CHECK-NEXT: [[COND:%.*]] = fcmp oeq double [[ABS]], 0x7FF0000000000000
; CHECK-NEXT: br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: [[CAST:%.*]] = bitcast double [[X]] to i64
-; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[CAST]], 3458764513820540928
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: ret i1 false
; CHECK: if.else:
; CHECK-NEXT: ret i1 false
;
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