[llvm] [RISCV] Use vcompress in deinterleave2 intrinsic lowering (PR #118325)

[Luke Lau via llvm-commits]

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@@ -10771,19 +10767,28 @@ SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
   }
 
   // For the indices, use the same SEW to avoid an extra vsetvli
+  // TODO: If container type is larger than m1, we can consider using a splat
+  // of a constant instead of the following sequence
+
+  // Create a vector of even indices {0, 1, 2, ...}
   MVT IdxVT = ConcatVT.changeVectorElementTypeToInteger();
-  // Create a vector of even indices {0, 2, 4, ...}
-  SDValue EvenIdx =
-      DAG.getStepVector(DL, IdxVT, APInt(IdxVT.getScalarSizeInBits(), 2));
-  // Create a vector of odd indices {1, 3, 5, ... }
-  SDValue OddIdx =
-      DAG.getNode(ISD::ADD, DL, IdxVT, EvenIdx, DAG.getConstant(1, DL, IdxVT));
-
-  // Gather the even and odd elements into two separate vectors
-  SDValue EvenWide = DAG.getNode(RISCVISD::VRGATHER_VV_VL, DL, ConcatVT,
-                                 Concat, EvenIdx, Passthru, Mask, VL);
-  SDValue OddWide = DAG.getNode(RISCVISD::VRGATHER_VV_VL, DL, ConcatVT,
-                                Concat, OddIdx, Passthru, Mask, VL);
+  SDValue StepVec = DAG.getStepVector(DL, IdxVT);
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lukel97 wrote:

A non-blocking idea: Instead of creating a step vector, can we fill up a mask register with a bitcasted LMUL=1 SEW=8 `vmv.v.i v0, 0b10101010`?  Not sure if this is a pain to implement though.

https://github.com/llvm/llvm-project/pull/118325