[llvm] [RISCV] Ensure the valid vtype during copyPhysReg (PR #118252)

[Piyou Chen via llvm-commits]

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@@ -421,6 +421,36 @@ void RISCVInstrInfo::copyPhysRegVector(
     auto MIB = BuildMI(MBB, MBBI, DL, get(Opc), ActualDstReg);
     bool UseVMV_V_I = RISCV::getRVVMCOpcode(Opc) == RISCV::VMV_V_I;
     bool UseVMV = UseVMV_V_I || RISCV::getRVVMCOpcode(Opc) == RISCV::VMV_V_V;
+
+    // Address https://github.com/llvm/llvm-project/issues/114518
+    // Make sure each whole RVVReg move has valid vtype.
+    unsigned Opcode = MIB->getOpcode();
+    if (UseVMV || Opcode == RISCV::VMV1R_V || Opcode == RISCV::VMV2R_V ||
+        Opcode == RISCV::VMV4R_V || Opcode == RISCV::VMV8R_V) {
+
+      // TODO: Data-flow analysis for vtype status could help avoid the
+      // redundant one.
+      bool NeedVSETIVLI = true;
+
+      for (auto &CurrMI : MBB) {
+        unsigned CurrMIOpcode = CurrMI.getOpcode();
+        if (CurrMIOpcode == RISCV::PseudoVSETIVLI ||
+            CurrMIOpcode == RISCV::PseudoVSETVLI ||
+            CurrMIOpcode == RISCV::PseudoVSETVLIX0)
+          NeedVSETIVLI = false;
+        else if (CurrMI.isInlineAsm())
+          NeedVSETIVLI = true;
+        else if (NeedVSETIVLI && &CurrMI == &*MIB) {
+          BuildMI(MBB, &*MIB, MIB->getDebugLoc(), get(RISCV::PseudoVSETIVLI))
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BeMg wrote:

Oh, yes. In this case, it will invalidate the vtype coming from the predecessor basic block. Maybe we could check the following RVV instructions in the same basic block without the explicit vsetvl to ensure there is a vtype from another basic block.

https://github.com/llvm/llvm-project/pull/118252