[llvm] a2cb208 - [RISCV] Fix a typo in a deinterleave test

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2024-12-02T17:02:47-08:00
New Revision: a2cb2088e766eaadfd6d573d379d5c692262e24f

URL: https://github.com/llvm/llvm-project/commit/a2cb2088e766eaadfd6d573d379d5c692262e24f
DIFF: https://github.com/llvm/llvm-project/commit/a2cb2088e766eaadfd6d573d379d5c692262e24f.diff

LOG: [RISCV] Fix a typo in a deinterleave test

This was supposed to test a deinterleave Factor=4, Offset=1, but had an
off by one in the shuffle mask.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
index 27e66690d1b1ee..6450174d44ca84 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
@@ -96,24 +96,25 @@ define void @deinterleave4_8_i8(ptr %in, ptr %out) {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
 ; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT:    vmv.v.i v9, -9
-; CHECK-NEXT:    vid.v v10
-; CHECK-NEXT:    li a0, 5
-; CHECK-NEXT:    vmadd.vx v10, a0, v9
+; CHECK-NEXT:    li a0, -1
+; CHECK-NEXT:    vsetivli zero, 8, e8, m1, ta, ma
+; CHECK-NEXT:    vslidedown.vi v9, v8, 8
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf2, ta, ma
+; CHECK-NEXT:    vslidedown.vi v10, v9, 4
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vwaddu.vv v11, v9, v10
+; CHECK-NEXT:    vwmaccu.vx v11, a0, v10
 ; CHECK-NEXT:    li a0, 34
 ; CHECK-NEXT:    vmv.v.i v0, 12
 ; CHECK-NEXT:    vmv.s.x v9, a0
-; CHECK-NEXT:    vcompress.vm v11, v8, v9
-; CHECK-NEXT:    vsetivli zero, 8, e8, m1, ta, ma
-; CHECK-NEXT:    vslidedown.vi v8, v8, 8
-; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT:    vrgather.vv v11, v8, v10, v0.t
-; CHECK-NEXT:    vse8.v v11, (a1)
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vcompress.vm v10, v8, v9
+; CHECK-NEXT:    vmerge.vvm v8, v10, v11, v0
+; CHECK-NEXT:    vse8.v v8, (a1)
 ; CHECK-NEXT:    ret
 entry:
   %0 = load <16 x i8>, ptr %in, align 1
-  %shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 5, i32 9, i32 14, i32 undef, i32 undef, i32 undef, i32 undef>
+  %shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 undef, i32 undef, i32 undef, i32 undef>
   store <8 x i8> %shuffle.i5, ptr %out, align 1
   ret void
 }