[llvm] de6d0d2 - [RISCV][GISel] Add FCLASS to onlyUsesFP for register bank selection (#118021)

[via llvm-commits]

Author: Luke Quinn
Date: 2024-12-02T11:19:08-08:00
New Revision: de6d0d2de0e2df72bd77f29d27addf13ebfbc997

URL: https://github.com/llvm/llvm-project/commit/de6d0d2de0e2df72bd77f29d27addf13ebfbc997
DIFF: https://github.com/llvm/llvm-project/commit/de6d0d2de0e2df72bd77f29d27addf13ebfbc997.diff

LOG: [RISCV][GISel] Add FCLASS to onlyUsesFP for register bank selection (#118021)

Bug fix FCLASS instruction in RISCV. The bug is due the fact that FCLASS
has an input float register and output GPR this caused reg bank select
regression.

Added: 
    llvm/test/CodeGen/RISCV/GlobalISel/float-fclass.ll

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 829c0ac92c52a4..a082b188676661 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -151,6 +151,7 @@ bool RISCVRegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
   switch (MI.getOpcode()) {
   case RISCV::G_FCVT_W_RV64:
   case RISCV::G_FCVT_WU_RV64:
+  case RISCV::G_FCLASS:
   case TargetOpcode::G_FPTOSI:
   case TargetOpcode::G_FPTOUI:
   case TargetOpcode::G_FCMP:
@@ -326,19 +327,21 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
     // Use FPR64 for s64 loads on rv32.
     if (GPRSize == 32 && Size.getFixedValue() == 64) {
       assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
-      OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
+      OpdsMapping[0] = getFPValueMapping(Size);
       break;
     }
 
     // Check if that load feeds fp instructions.
     // In that case, we want the default mapping to be on FPR
     // instead of blind map every scalar to GPR.
-    if (anyUseOnlyUseFP(MI.getOperand(0).getReg(), MRI, TRI))
+    if (anyUseOnlyUseFP(MI.getOperand(0).getReg(), MRI, TRI)) {
       // If we have at least one direct use in a FP instruction,
       // assume this was a floating point load in the IR. If it was
       // not, we would have had a bitcast before reaching that
       // instruction.
-      OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
+      OpdsMapping[0] = getFPValueMapping(Size);
+      break;
+    }
 
     break;
   }

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/float-fclass.ll b/llvm/test/CodeGen/RISCV/GlobalISel/float-fclass.ll
new file mode 100644
index 00000000000000..b846302c8a3c05
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/float-fclass.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+
+; RUN: llc -mtriple=riscv32 -mattr=+f -global-isel \
+; RUN:   < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+f -global-isel \
+; RUN:   < %s | FileCheck %s --check-prefixes=CHECK
+
+define i1 @fpclass(ptr %x) {
+; CHECK-LABEL: fpclass:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    flw fa5, 0(a0)
+; CHECK-NEXT:    fclass.s a0, fa5
+; CHECK-NEXT:    andi a0, a0, 927
+; CHECK-NEXT:    snez a0, a0
+; CHECK-NEXT:    ret
+  %a = load float, ptr %x
+  %cmp = call i1 @llvm.is.fpclass.f32(float %a, i32 639)
+  ret i1 %cmp
+}