[llvm] [RISCV] Clear vill for whole vector register moves in vsetvli insertion (PR #118283)

[Philip Reames via llvm-commits]

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@@ -195,6 +195,14 @@ static bool hasUndefinedPassthru(const MachineInstr &MI) {
   return UseMO.getReg() == RISCV::NoRegister || UseMO.isUndef();
 }
 
+/// Return true if \p MI is a copy that will be lowered to one or more vmvNr.vs.
+static bool isVectorCopy(const TargetRegisterInfo *TRI,
+                         const MachineInstr &MI) {
+  return MI.isCopy() && MI.getOperand(0).getReg().isPhysical() &&
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preames wrote:

Where do we lower from the segmented load/store register classes?  I know those survive through vector register allocation (as in we have spill fill supoort), do we need to handle them here?

https://github.com/llvm/llvm-project/pull/118283