[llvm] SystemZ: Regenerate baseline checks for some coalescer tests (PR #118322)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 2 08:44:32 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-systemz
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
These were missing -NEXT checks and also had some dead checks.
Also switch a test to actually check the output.
---
Full diff: https://github.com/llvm/llvm-project/pull/118322.diff
4 Files Affected:
- (modified) llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir (+4-5)
- (modified) llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir (+23-20)
- (modified) llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir (+57-43)
- (modified) llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir (+36-51)
``````````diff
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
index f7b58f04fd7bad..e3207df799449a 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update-remat.mir
@@ -29,13 +29,12 @@ tracksRegLiveness: true
body: |
bb.0:
- ; CHECK-LABEL
; CHECK-LABEL: name: main
; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 25
- ; CHECK: CHIMux [[LGHI]].subreg_l32, 0, implicit-def $cc
- ; CHECK: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 25
- ; CHECK: undef [[LGHI1]].subreg_l32:gr64bit = MSFI [[LGHI1]].subreg_l32, -117440512
- ; CHECK: Return implicit [[LGHI1]].subreg_l32
+ ; CHECK-NEXT: CHIMux [[LGHI]].subreg_l32, 0, implicit-def $cc
+ ; CHECK-NEXT: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 25
+ ; CHECK-NEXT: undef [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = MSFI [[LGHI1]].subreg_l32, -117440512
+ ; CHECK-NEXT: Return implicit [[LGHI1]].subreg_l32
%0:gr64bit = LGHI 25
%1:gr32bit = COPY %0.subreg_l32
%1:gr32bit = MSFI %1, -117440512
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
index bf5855010bf90b..c805d31aa11c62 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir
@@ -25,12 +25,12 @@ body: |
; CHECK-LABEL: name: main
; CHECK: [[LGHI:%[0-9]+]]:gr64bit = LGHI 43
- ; CHECK: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43
- ; CHECK: [[LGHI1]].subreg_l32:gr64bit = MSR [[LGHI1]].subreg_l32, [[LGHI1]].subreg_l32
- ; CHECK: [[LGHI1]].subreg_l32:gr64bit = AHIMux [[LGHI1]].subreg_l32, 9, implicit-def dead $cc
- ; CHECK: undef %3.subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI1]].subreg_l32
- ; CHECK: [[DLGR:%[0-9]+]]:gr128bit = DLGR [[DLGR]], [[LGHI]]
- ; CHECK: Return implicit [[DLGR]]
+ ; CHECK-NEXT: [[LGHI1:%[0-9]+]]:gr64bit = LGHI 43
+ ; CHECK-NEXT: undef [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = MSR [[LGHI1]].subreg_l32, [[LGHI1]].subreg_l32
+ ; CHECK-NEXT: [[LGHI1:%[0-9]+]].subreg_l32:gr64bit = AHIMux [[LGHI1]].subreg_l32, 9, implicit-def dead $cc
+ ; CHECK-NEXT: undef [[LGFI:%[0-9]+]].subreg_l64:gr128bit = LGFI -245143785, implicit [[LGHI1]].subreg_l32
+ ; CHECK-NEXT: [[LGFI:%[0-9]+]]:gr128bit = DLGR [[LGFI]], [[LGHI]]
+ ; CHECK-NEXT: Return implicit [[LGFI]]
%0:gr64bit = LGHI 43
%1:gr32bit = COPY %0.subreg_l32
%1:gr32bit = MSR %1, %1
@@ -55,20 +55,23 @@ liveins: []
body: |
; CHECK-LABEL: name: segfault
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[LGHI:%[0-9]+]]:addr64bit = LGHI 0
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: ADJCALLSTACKDOWN 0, 0
- ; CHECK: [[LGFR:%[0-9]+]]:gr64bit = LGFR [[LGHI]].subreg_l32
- ; CHECK: $r2d = LGHI 123
- ; CHECK: $r3d = LGHI 0
- ; CHECK: $r4d = LGHI 0
- ; CHECK: $r5d = COPY [[LGFR]]
- ; CHECK: KILL killed $r2d, killed $r3d, killed $r4d, $r5d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
- ; CHECK: ADJCALLSTACKUP 0, 0
- ; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg
- ; CHECK: J %bb.1
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = LGHI 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0
+ ; CHECK-NEXT: [[LGFR:%[0-9]+]]:gr64bit = LGFR [[LGHI]].subreg_l32
+ ; CHECK-NEXT: $r2d = LGHI 123
+ ; CHECK-NEXT: $r3d = LGHI 0
+ ; CHECK-NEXT: $r4d = LGHI 0
+ ; CHECK-NEXT: $r5d = COPY [[LGFR]]
+ ; CHECK-NEXT: KILL killed $r2d, killed $r3d, killed $r4d, $r5d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
+ ; CHECK-NEXT: ADJCALLSTACKUP 0, 0
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = nuw nsw LA [[LGHI]], 1, $noreg
+ ; CHECK-NEXT: J %bb.1
bb.0:
successors: %bb.1(0x80000000)
diff --git a/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir b/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir
index b1a0a309e1e20a..cd8f14b28844b4 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal-undef-lane-4-rm-cp-commuting-def.mir
@@ -15,56 +15,70 @@
# only partial defined before being fully copied.
#
# PR40215.
+
+
+# The coalescer should have been able to swap the operands of
+# the OR, hence eliminating the copy of %20 and %18.
+# This is also visible here because the ROSBG operand was LHS
+# before the coalescer, now it is RHS.
---
name: main
alignment: 16
tracksRegLiveness: true
-machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: main
; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[LGHI:%[0-9]+]]:addr64bit = LGHI -30
- ; CHECK: [[LHIMux:%[0-9]+]]:grx32bit = LHIMux 1
- ; CHECK: [[LHIMux1:%[0-9]+]]:grx32bit = LHIMux 0
- ; CHECK: undef %20.subreg_l32:gr64bit = IMPLICIT_DEF
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.3(0x00000001), %bb.4(0x7fffffff)
- ; CHECK: CHIMux [[LHIMux]], 0, implicit-def $cc
- ; CHECK: BRC 14, 6, %bb.3, implicit killed $cc
- ; CHECK: J %bb.4
- ; CHECK: bb.2:
- ; CHECK: successors:
- ; CHECK: STMux %20.subreg_l32, undef %8:addr64bit, 0, $noreg :: (store (s32) into `ptr undef`)
- ; CHECK: bb.3:
- ; CHECK: successors:
- ; CHECK: bb.4:
- ; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000)
- ; CHECK: [[LAY:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19838, $noreg
- ; CHECK: [[LAY1:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19840, $noreg
- ; CHECK: [[LAY2:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19844, $noreg
- ; CHECK: [[OGR:%[0-9]+]]:gr64bit = OGR [[OGR]], [[LAY]], implicit-def dead $cc
- ; CHECK: undef %19.subreg_l32:gr64bit = AHIMuxK [[LGHI]].subreg_l32, 19843, implicit-def dead $cc
- ; CHECK: [[ROSBG:%[0-9]+]]:gr64bit = ROSBG [[ROSBG]], [[OGR]], 32, 63, 0, implicit-def dead $cc
- ; The coalescer should have been able to swap the operands of
- ; the OR, hence eliminating the copy of %20 and %18.
- ; This is also visible here because the ROSBG operand was LHS
- ; before the coalescer, now it is RHS.
- ; CHECK: %20.subreg_l32:gr64bit = OR %20.subreg_l32, [[ROSBG]].subreg_l32, implicit-def dead $cc
- ; CHECK: [[ROSBG1:%[0-9]+]]:gr64bit = ROSBG [[ROSBG1]], [[LAY1]], 32, 63, 0, implicit-def dead $cc
- ; CHECK: CHIMux [[LHIMux1]], 0, implicit-def $cc
- ; CHECK: BRC 14, 6, %bb.6, implicit killed $cc
- ; CHECK: J %bb.5
- ; CHECK: bb.5:
- ; CHECK: successors: %bb.6(0x80000000)
- ; CHECK: bb.6:
- ; CHECK: successors: %bb.2(0x00000001), %bb.7(0x7fffffff)
- ; CHECK: [[LGHI]]:addr64bit = nuw nsw LA [[LGHI]], 6, $noreg
- ; CHECK: CGHI [[LGHI]], 0, implicit-def $cc
- ; CHECK: BRC 14, 8, %bb.2, implicit killed $cc
- ; CHECK: bb.7:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: J %bb.1
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = LGHI -30
+ ; CHECK-NEXT: [[LHIMux:%[0-9]+]]:grx32bit = LHIMux 1
+ ; CHECK-NEXT: [[LHIMux1:%[0-9]+]]:grx32bit = LHIMux 0
+ ; CHECK-NEXT: undef [[DEF:%[0-9]+]].subreg_l32:gr64bit = IMPLICIT_DEF
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.3(0x00000001), %bb.4(0x7fffffff)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: CHIMux [[LHIMux]], 0, implicit-def $cc
+ ; CHECK-NEXT: BRC 14, 6, %bb.3, implicit killed $cc
+ ; CHECK-NEXT: J %bb.4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: successors:
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: STMux [[DEF]].subreg_l32, undef %8:addr64bit, 0, $noreg :: (store (s32) into `ptr undef`)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.3:
+ ; CHECK-NEXT: successors:
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.4:
+ ; CHECK-NEXT: successors: %bb.5(0x30000000), %bb.6(0x50000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LAY:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19838, $noreg
+ ; CHECK-NEXT: [[LAY1:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19840, $noreg
+ ; CHECK-NEXT: [[LAY2:%[0-9]+]]:gr64bit = LAY [[LGHI]], 19844, $noreg
+ ; CHECK-NEXT: [[LAY2:%[0-9]+]]:gr64bit = OGR [[LAY2]], [[LAY]], implicit-def dead $cc
+ ; CHECK-NEXT: undef [[AHIMuxK:%[0-9]+]].subreg_l32:gr64bit = AHIMuxK [[LGHI]].subreg_l32, 19843, implicit-def dead $cc
+ ; CHECK-NEXT: [[AHIMuxK:%[0-9]+]]:gr64bit = ROSBG [[AHIMuxK]], [[LAY2]], 32, 63, 0, implicit-def dead $cc
+ ; CHECK-NEXT: [[DEF:%[0-9]+]].subreg_l32:gr64bit = OR [[DEF]].subreg_l32, [[AHIMuxK]].subreg_l32, implicit-def dead $cc
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64bit = ROSBG [[DEF]], [[LAY1]], 32, 63, 0, implicit-def dead $cc
+ ; CHECK-NEXT: CHIMux [[LHIMux1]], 0, implicit-def $cc
+ ; CHECK-NEXT: BRC 14, 6, %bb.6, implicit killed $cc
+ ; CHECK-NEXT: J %bb.5
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.5:
+ ; CHECK-NEXT: successors: %bb.6(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.6:
+ ; CHECK-NEXT: successors: %bb.2(0x00000001), %bb.7(0x7fffffff)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LGHI:%[0-9]+]]:addr64bit = nuw nsw LA [[LGHI]], 6, $noreg
+ ; CHECK-NEXT: CGHI [[LGHI]], 0, implicit-def $cc
+ ; CHECK-NEXT: BRC 14, 8, %bb.2, implicit killed $cc
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.7:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: J %bb.1
bb.0:
%6:gr64bit = LGHI -30
%8:grx32bit = LHIMux 1
diff --git a/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir b/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir
index eb1fd4e9c14879..3ee857b7b1b183 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir
+++ b/llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir
@@ -1,55 +1,38 @@
-# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -O3 -start-before=livevars %s -o /dev/null 2>&1
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=livevars -stop-after=register-coalescer %s -o - | FileCheck %s
# Test that coalesing of an empty live range (undef) does not cause failure.
---- |
- define dso_local void @fun(ptr %src, ptr %dst) #0 {
- %1 = sdiv i64 poison, poison
- %2 = load i32, ptr %src, align 4
- br i1 poison, label %6, label %3
-
- 3: ; preds = %0
- %4 = trunc i64 %1 to i32
- %5 = udiv i32 %4, %2
- br label %6
-
- 6: ; preds = %3, %0
- %7 = phi i32 [ %5, %3 ], [ 1, %0 ]
- store i32 %7, ptr %dst, align 4
- ret void
- }
-
-...
---
name: fun
-alignment: 16
tracksRegLiveness: true
-registers:
- - { id: 0, class: gr64bit }
- - { id: 1, class: gr32bit }
- - { id: 2, class: grx32bit }
- - { id: 3, class: grx32bit }
- - { id: 4, class: addr64bit }
- - { id: 5, class: addr64bit }
- - { id: 6, class: grx32bit }
- - { id: 7, class: grx32bit }
- - { id: 8, class: grx32bit }
- - { id: 9, class: gr64bit }
- - { id: 10, class: gr64bit }
- - { id: 11, class: gr128bit }
- - { id: 12, class: gr128bit }
- - { id: 13, class: gr128bit }
- - { id: 14, class: gr128bit }
- - { id: 15, class: gr64bit }
-liveins:
- - { reg: '$r2d', virtual-reg: '%4' }
- - { reg: '$r3d', virtual-reg: '%5' }
-frameInfo:
- maxAlignment: 1
-machineFunctionInfo: {}
body: |
- bb.0 (%ir-block.0):
+ ; CHECK-LABEL: name: fun
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $r2d, $r3d
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:addr64bit = COPY $r3d
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:addr64bit = COPY $r2d
+ ; CHECK-NEXT: [[LHIMux:%[0-9]+]]:grx32bit = LHIMux 1
+ ; CHECK-NEXT: [[LHIMux1:%[0-9]+]]:grx32bit = LHIMux 0
+ ; CHECK-NEXT: CHIMux [[LHIMux1]], 0, implicit-def $cc
+ ; CHECK-NEXT: BRC 14, 6, %bb.2, implicit killed $cc
+ ; CHECK-NEXT: J %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LMux:%[0-9]+]]:gr32bit = LMux [[COPY1]], 0, $noreg :: (load (s32))
+ ; CHECK-NEXT: undef [[LLILL:%[0-9]+]].subreg_h64:gr128bit = LLILL 0
+ ; CHECK-NEXT: [[LLILL:%[0-9]+]]:gr128bit = DLR [[LLILL]], [[LMux]]
+ ; CHECK-NEXT: [[LHIMux:%[0-9]+]]:grx32bit = COPY [[LLILL]].subreg_ll32
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: STMux [[LHIMux]], [[COPY]], 0, $noreg :: (store (s32))
+ ; CHECK-NEXT: Return
+ bb.0:
liveins: $r2d, $r3d
-
+
%5:addr64bit = COPY $r3d
%4:addr64bit = COPY $r2d
%6:grx32bit = LHIMux 1
@@ -57,18 +40,20 @@ body: |
CHIMux killed %7, 0, implicit-def $cc
BRC 14, 6, %bb.2, implicit $cc
J %bb.1
-
- bb.1 (%ir-block.3):
- %1:gr32bit = LMux %4, 0, $noreg :: (load (s32) from %ir.src)
+
+ bb.1:
+ %1:gr32bit = LMux %4, 0, $noreg :: (load (s32))
%15:gr64bit = LLILL 0
%14:gr128bit = INSERT_SUBREG undef %13:gr128bit, %15, %subreg.subreg_h64
%11:gr128bit = INSERT_SUBREG %14, undef %9:gr64bit, %subreg.subreg_l64
%12:gr128bit = DLR %11, %1
%2:grx32bit = COPY %12.subreg_ll32
-
- bb.2 (%ir-block.6):
+
+ bb.2:
%3:grx32bit = PHI %6, %bb.0, %2, %bb.1
- STMux %3, %5, 0, $noreg :: (store (s32) into %ir.dst)
+ STMux %3, %5, 0, $noreg :: (store (s32))
Return
...
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# CHECK: {{.*}}
``````````
</details>
https://github.com/llvm/llvm-project/pull/118322
More information about the llvm-commits
mailing list