[llvm] [AArch64] Improve operand sinking for mul instructions (PR #116604)

[David Green via llvm-commits]

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@@ -5168,26 +5168,46 @@ bool AArch64TTIImpl::isProfitableToSinkOperands(
     return false;
   }
   case Instruction::Mul: {
+    auto ShouldSinkSplatForIndexedVariant = [](Value *V) {
+      auto *Ty = cast<VectorType>(V->getType());
+      // For SVE the lane-indexing is within 128-bits, so we can't fold splats.
+      if (Ty->isScalableTy())
+        return false;
+
+      // Indexed variants of Mul exist for i16 and i32 element types only.
+      auto ElemVT = MVT::getVT(Ty->getElementType(), /*HandleUnknown=*/true);
+      return (ElemVT == MVT::i16 || ElemVT == MVT::i32);
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davemgreen wrote:

It is possible to avoid the MVT types by checking `Ty->getScalarSizeInBits() == 16 || == 32`.

https://github.com/llvm/llvm-project/pull/116604