[llvm] [RISCV] Clear vill for whole vector register moves in vsetvli insertion (PR #118283)

[Luke Lau via llvm-commits]

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@@ -1208,6 +1233,17 @@ static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
 // legal for MI, but may not be the state requested by MI.
 void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
                                         const MachineInstr &MI) const {
+  if (isVectorCopy(ST->getRegisterInfo(), MI) &&
+      (Info.isUnknown() || !Info.isValid() || Info.hasSEWLMULRatioOnly())) {
+    // Use an arbitrary but valid AVL and VTYPE so vill will be cleared. It may
+    // be coalesced into another vsetvli since we won't demand any fields.
+    VSETVLIInfo NewInfo; // Need a new VSETVLIInfo to clear SEWLMULRatioOnly
+    NewInfo.setAVLImm(0);
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lukel97 wrote:

We might also want to use 1 as the AVL. I have a feeling some microarchitectures might special case vl=0, can anyone confirm?

https://github.com/llvm/llvm-project/pull/118283