[llvm] [DAGISel][ARM] Fix vector truncate combine for big-endian (PR #118101)

[Oliver Stannard via llvm-commits]

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@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=armebv7-unknown-none-eabihf -mattr=+neon < %s | FileCheck %s
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ostannard wrote:

I've had a search and can't find any existing tests which cover this. The only way I've been able to hit this code path is with operations on `<8 x i64>`, which is very over-sized for NEON so gets expanded multiple times.

https://github.com/llvm/llvm-project/pull/118101